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Merge branch 'YosysHQ:main' into master

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Akash Levy 2024-08-19 17:12:02 -07:00 • committed by GitHub
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tests/opt/bug4413.ys Normal file
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read_verilog <<EOT
module top(
input wire shift,
input wire [4:0] data,
output wire out
);
wire [1:0] shift2 = shift - 1'b1;
assign out = data >> shift2;
endmodule
EOT
equiv_opt -assert peepopt