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Improved sat generator and sat_solve pass

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Clifford Wolf 2013-06-07 14:37:33 +02:00
parent 46fbe9d262
commit 56b593b91c
6 changed files with 57 additions and 15 deletions
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passes/sat/example.ys
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@ -1,3 +1,3 @@
read_verilog example.v
techmap; opt
techmap; opt; abc; opt
sat_solve -show a -set y 1'b1