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Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp

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This commit is contained in:
Eddie Hung 2019-07-16 14:18:36 -07:00
commit 569cd66764
4 changed files with 35 additions and 27 deletions
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techlibs/xilinx/cells_sim.v
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@ -516,7 +516,7 @@ module DSP48E1 (
if (PCIN != 48'b0) $fatal(1, "Unsupported PCIN value");
if (CARRYIN != 1'b0) $fatal(1, "Unsupported CARRYIN value");
`endif
Pr[42:0] <= Ar[24:0] * Br;
Pr[42:0] <= $signed(Ar[24:0]) * $signed(Br);
end
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