mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-28 08:58:45 +00:00
Code Activity

abc9_ops: -prep_lut and -write_lut to auto-generate LUT library

Browse source
This commit is contained in:
Eddie Hung 2020-02-11 08:34:13 -08:00
parent ab8826ae36
commit 5643c1b8c5
4 changed files with 200 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

6
techlibs/xilinx/synth_xilinx.cc
View file

@ -354,7 +354,7 @@ struct SynthXilinxPass : public ScriptPass
std::string read_args;
if (vpr)
read_args += " -D_EXPLICIT_CARRY";
read_args += " -lib +/xilinx/cells_sim.v";
read_args += " -lib -specify +/xilinx/cells_sim.v";
run("read_verilog" + read_args);
run("read_verilog -lib +/xilinx/cells_xtra.v");
@ -627,9 +627,7 @@ struct SynthXilinxPass : public ScriptPass
else
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str());
if (nowidelut)
abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
else
abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
abc9_opts += stringf(" -maxlut %d", lut_size_s);
if (dff_mode)
abc9_opts += " -dff";
run("abc9" + abc9_opts);