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Added defparam support to Verilog/AST frontend
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parent
3b294b3912
commit
56432a920f
7 changed files with 79 additions and 13 deletions
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@ -103,7 +103,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage)
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}
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// activate const folding if this is anything that must be evaluated statically (ranges, parameters, attributes, etc.)
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if (type == AST_WIRE || type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_PARASET || type == AST_RANGE || type == AST_PREFIX)
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if (type == AST_WIRE || type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_DEFPARAM || type == AST_PARASET || type == AST_RANGE || type == AST_PREFIX)
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const_fold = true;
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if (type == AST_IDENTIFIER && current_scope.count(str) > 0 && (current_scope[str]->type == AST_PARAMETER || current_scope[str]->type == AST_LOCALPARAM))
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const_fold = true;
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@ -163,7 +163,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage)
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}
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wires_are_incompatible:
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if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_GENVAR ||
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node->type == AST_MEMORY || node->type == AST_FUNCTION || node->type == AST_TASK) {
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node->type == AST_MEMORY || node->type == AST_FUNCTION || node->type == AST_TASK || node->type == AST_CELL) {
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backup_scope[node->str] = current_scope[node->str];
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current_scope[node->str] = node;
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}
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@ -224,6 +224,22 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage)
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if (type == AST_MODULE)
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current_scope.clear();
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// convert defparam nodes to cell parameters
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if (type == AST_DEFPARAM && !str.empty()) {
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size_t pos = str.rfind('.');
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if (pos == std::string::npos)
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log_error("Defparam `%s' does not contain a dot (module/parameter seperator) at %s:%d!\n",
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RTLIL::id2cstr(str.c_str()), filename.c_str(), linenum);
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std::string modname = str.substr(0, pos), paraname = "\\" + str.substr(pos+1);
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if (current_scope.count(modname) == 0 || current_scope.at(modname)->type != AST_CELL)
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log_error("Can't find cell for defparam `%s . %s` at %s:%d!\n", RTLIL::id2cstr(modname), RTLIL::id2cstr(paraname), filename.c_str(), linenum);
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AstNode *cell = current_scope.at(modname), *paraset = clone();
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cell->children.insert(cell->children.begin() + 1, paraset);
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paraset->type = AST_PARASET;
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paraset->str = paraname;
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str.clear();
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}
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// resolve constant prefixes
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if (type == AST_PREFIX) {
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if (children[0]->type != AST_CONSTANT) {
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