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Added defparam support to Verilog/AST frontend

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This commit is contained in:
Clifford Wolf 2013-07-04 14:12:33 +02:00
parent 3b294b3912
commit 56432a920f
7 changed files with 79 additions and 13 deletions
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frontends/ast/genrtlil.cc
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@ -531,6 +531,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint)
case AST_AUTOWIRE:
case AST_PARAMETER:
case AST_LOCALPARAM:
case AST_DEFPARAM:
case AST_GENVAR:
case AST_GENFOR:
case AST_GENBLOCK: