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Added test cases from 2012 paper on comparison of foss verilog synthesis tools

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Clifford Wolf 2013-03-31 11:17:56 +02:00
parent 04843bdcbe
commit 5640b7d607
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tests/simple/forgen01.v Normal file
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module uut_forgen01(a, y);
input [4:0] a;
output y;
integer i, j;
reg [31:0] lut;
initial begin
for (i = 0; i < 32; i = i+1) begin
lut[i] = i > 1;
for (j = 2; j*j <= i; j = j+1)
if (i % j == 0)
lut[i] = 0;
end
end
assign y = lut[a];
endmodule