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Added test cases from 2012 paper on comparison of foss verilog synthesis tools

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Clifford Wolf 2013-03-31 11:17:56 +02:00
parent 04843bdcbe
commit 5640b7d607
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tests/simple/arrays01.v Normal file
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module uut_arrays01(clock, we, addr, wr_data, rd_data);
input clock, we;
input [3:0] addr, wr_data;
output [3:0] rd_data;
reg [3:0] rd_data;
reg [3:0] memory [15:0];
always @(posedge clock) begin
if (we)
memory[addr] <= wr_data;
rd_data <= memory[addr];
end
endmodule