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Added test cases from 2012 paper on comparison of foss verilog synthesis tools

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Clifford Wolf 2013-03-31 11:17:56 +02:00
parent 04843bdcbe
commit 5640b7d607
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tests/simple/always03.v Normal file
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module uut_always03(clock, in1, in2, in3, in4, in5, in6, in7, out1, out2, out3);
input clock, in1, in2, in3, in4, in5, in6, in7;
output out1, out2, out3;
reg out1, out2, out3;
always @(posedge clock) begin
out1 = in1;
if (in2)
out1 = !out1;
out2 <= out1;
if (in3)
out2 <= out2;
if (in4)
if (in5)
out3 <= in6;
else
out3 <= in7;
out1 = out1 ^ out2;
end
endmodule