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Added test cases from 2012 paper on comparison of foss verilog synthesis tools

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Clifford Wolf 2013-03-31 11:17:56 +02:00
parent 04843bdcbe
commit 5640b7d607
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tests/simple/always01.v Normal file
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module uut_always01(clock, reset, count);
input clock, reset;
output [3:0] count;
reg [3:0] count;
always @(posedge clock)
count <= reset ? 0 : count + 1;
endmodule