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Fix wide shift count fold.

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nella 2026-07-07 15:04:57 +02:00
parent 8a2499b544
commit 5628dff0bd
3 changed files with 65 additions and 1 deletions
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30
tests/opt/opt_expr_shift.ys
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@ -114,6 +114,36 @@ select -assert-none t:$shiftx
design -reset
read_verilog <<EOT
module top (
input wire [3:0] in,
output wire [7:0] shl,
output wire [7:0] shr,
output wire [7:0] sshl,
output wire [7:0] sshr,
);
assign shl = in << 33'h0ffffffff;
assign shr = in >> 33'h0ffffffff;
assign sshl = in <<< 33'h0ffffffff;
assign sshr = in >>> 33'h0ffffffff;
endmodule
EOT
select -assert-count 1 t:$shl
select -assert-count 1 t:$shr
select -assert-count 1 t:$sshl
select -assert-count 1 t:$sshr
equiv_opt -assert opt_expr
design -load postopt
select -assert-none t:$shl
select -assert-none t:$shr
select -assert-none t:$sshl
select -assert-none t:$sshr
design -reset
read_verilog <<EOT
module top (
input wire [3:0] in,