From dc693652583e83db82cc95c407e4778e640473d7 Mon Sep 17 00:00:00 2001 From: Asherah Connor Date: Sun, 26 May 2024 18:21:45 +0300 Subject: [PATCH 01/37] cxxrtl: failing test: unconnected blackbox outputs don't compile. --- tests/cxxrtl/run-test.sh | 4 ++++ tests/cxxrtl/test_unconnected_output.v | 24 ++++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 tests/cxxrtl/test_unconnected_output.v diff --git a/tests/cxxrtl/run-test.sh b/tests/cxxrtl/run-test.sh index 89de71c6b..fd11a3783 100755 --- a/tests/cxxrtl/run-test.sh +++ b/tests/cxxrtl/run-test.sh @@ -11,3 +11,7 @@ run_subtest () { run_subtest value run_subtest value_fuzz + +# Compile-only test. +../../yosys -p "read_verilog test_unconnected_output.v; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc" +${CC:-gcc} -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc diff --git a/tests/cxxrtl/test_unconnected_output.v b/tests/cxxrtl/test_unconnected_output.v new file mode 100644 index 000000000..84d172bdb --- /dev/null +++ b/tests/cxxrtl/test_unconnected_output.v @@ -0,0 +1,24 @@ +(* cxxrtl_blackbox *) +module blackbox(...); + (* cxxrtl_edge = "p" *) + input clk; + + (* cxxrtl_sync *) + output [7:0] out1; + + (* cxxrtl_sync *) + output [7:0] out2; +endmodule + +module unconnected_output( + input clk, + in, + output out +); + blackbox bb ( + .clock (clock), + .in (in), + .out1 (out), + .out2 (/* unconnected */), + ); +endmodule From e97c36d4c4189d57eb84e8d6f57de85dfdd551f8 Mon Sep 17 00:00:00 2001 From: Asherah Connor Date: Sun, 26 May 2024 18:31:32 +0300 Subject: [PATCH 02/37] cxxrtl: don't emit syncs for empty lhs. --- backends/cxxrtl/cxxrtl_backend.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 9ddbd33b0..8dc14863d 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -1138,7 +1138,7 @@ struct CxxrtlWorker { f << indent << "// cell " << cell->name.str() << " syncs\n"; for (auto conn : cell->connections()) if (cell->output(conn.first)) - if (is_cxxrtl_sync_port(cell, conn.first)) { + if (is_cxxrtl_sync_port(cell, conn.first) && !conn.second.empty()) { f << indent; dump_sigspec_lhs(conn.second, for_debug); f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n"; From 54d5e567459e6ba39114d5cebf4291705fe2f1fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jean-Fran=C3=A7ois=20Nguyen?= Date: Fri, 7 Jun 2024 05:15:38 +0200 Subject: [PATCH 03/37] cxxrtl: fix `debug_info()` deprecation message. --- backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h index 057d34cf9..70f30e7f9 100644 --- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h @@ -1582,7 +1582,7 @@ struct module { // Compatibility method. #if __has_attribute(deprecated) - __attribute__((deprecated("Use `debug_info(path, &items, /*scopes=*/nullptr);` instead. (`path` could be \"top \".)"))) + __attribute__((deprecated("Use `debug_info(&items, /*scopes=*/nullptr, path);` instead. (`path` could be \"top \".)"))) #endif void debug_info(debug_items &items, std::string path) { debug_info(&items, /*scopes=*/nullptr, path); From b0ab1cf8c3a2d864b6ce0675a1235e9293e5730e Mon Sep 17 00:00:00 2001 From: Mike Inouye Date: Fri, 7 Jun 2024 22:51:28 +0000 Subject: [PATCH 04/37] Fix memory leak in verific file parsing. Signed-off-by: Mike Inouye --- frontends/verific/verific.cc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index b4b0664d3..f7c2cefd2 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3510,6 +3510,12 @@ struct VerificPass : public Pass { verific_error_msg.clear(); log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); } + char* fn; + int i = 0; + + FOREACH_ARRAY_ITEM(&file_names, i, fn) { + free(fn); + } set_modules_to_blackbox(map, work, flag_lib); verific_import_pending = true; goto check_error; From 82783646e57264e82ac29ade76dc2bee6c416667 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 8 Jun 2024 00:17:45 +0000 Subject: [PATCH 05/37] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 0c2e11953..da8aac473 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LIBS += -lrt endif endif -YOSYS_VER := 0.42+0 +YOSYS_VER := 0.42+2 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From b593f5c01ce993a16fbba8197d85b58993302239 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 10 Jun 2024 15:51:43 +0200 Subject: [PATCH 06/37] Update the overview comment in `ast.h` --- frontends/ast/ast.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index f05b568be..59a393e08 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -17,12 +17,7 @@ * * --- * - * This is the AST frontend library. - * - * The AST frontend library is not a frontend on it's own but provides a - * generic abstract syntax tree (AST) abstraction for HDL code and can be - * used by HDL frontends. See "ast.h" for an overview of the API and the - * Verilog frontend for an usage example. + * This is support code for the Verilog frontend at frontends/verilog * */ From ef90458820461988f389e6b7f069956fd4156673 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 11 Jun 2024 00:17:10 +0000 Subject: [PATCH 07/37] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index da8aac473..92fce6c7d 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LIBS += -lrt endif endif -YOSYS_VER := 0.42+2 +YOSYS_VER := 0.42+10 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From df4e630ac49274336b3f1ac6a1ad9e1226a41ed6 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 11 Jun 2024 13:17:56 +1200 Subject: [PATCH 08/37] Docs: Add section for script parsing Document `!` and `:`. Add warning that semicolons need spaces. --- .../getting_started/scripting_intro.rst | 38 +++++++++++++++++-- 1 file changed, 34 insertions(+), 4 deletions(-) diff --git a/docs/source/getting_started/scripting_intro.rst b/docs/source/getting_started/scripting_intro.rst index bda76b74e..a6b4cb6bb 100644 --- a/docs/source/getting_started/scripting_intro.rst +++ b/docs/source/getting_started/scripting_intro.rst @@ -8,10 +8,40 @@ file format and how you can make your own synthesis scripts. Yosys script files typically use the :file:`.ys` extension and contain a set of commands for Yosys to run sequentially. These commands are the same ones we were using on the previous page like :cmd:ref:`read_verilog` and -:cmd:ref:`hierarchy`. As with the interactive shell, each command consists of -the command name, and an optional whitespace separated list of arguments. -Commands are terminated with the newline character, or by a semicolon (;). Empty -lines, and lines starting with the hash sign (#), are ignored. +:cmd:ref:`hierarchy`. + +Script parsing +~~~~~~~~~~~~~~ + +As with the interactive shell, each command consists of the command name, and an +optional whitespace separated list of arguments. Commands are terminated with +the newline character, and anything after a hash sign ``#`` is a comment (i.e. +it is ignored). + +It is also possible to terminate commands with a semicolon ``;``. This is +particularly useful in conjunction with the ``-p `` command line +option, where ```` can be a string with multiple commands separated by +semicolon. In-line comments can also be made with the colon ``:``, where the end +of the comment is a semicolon ``;`` or a new line. + +.. code-block:: + :caption: Using the ``-p`` option + + $ yosys -p "read_verilog fifo.v; :this is a comment; prep" + +.. warning:: + + The space after the semicolon is required for correct parsing. ``log a;log + b;`` for example will display ``a;log b`` instead of ``a`` and ``b`` as might + be expected. + +Another special character that can be used in Yosys scripts is the bang ``!``. +Anything after the bang will be executed as a shell command. This can only be +terminated with a new line. Any semicolons, hashes, or other special characters +will be passed to the shell. If an error code is returned from the shell it +will be raised by Yosys. :cmd:ref:`exec` provides a much more flexible way of +executing commands, allowing the output to be logged and more control over when +to generate errors. The synthesis starter script ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ From 7f89a45ad724888b111227127b14a48e0b5e48ad Mon Sep 17 00:00:00 2001 From: Marian Buschsieweke Date: Mon, 10 Jun 2024 21:27:19 +0200 Subject: [PATCH 09/37] cxxxrtl: fix use of format specifiers in test This fix a few instances of incorrect (and non-portable) use of format specifiers. --- tests/cxxrtl/test_value_fuzz.cc | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/tests/cxxrtl/test_value_fuzz.cc b/tests/cxxrtl/test_value_fuzz.cc index a7bbb293a..7e8fbb0a9 100644 --- a/tests/cxxrtl/test_value_fuzz.cc +++ b/tests/cxxrtl/test_value_fuzz.cc @@ -1,3 +1,4 @@ +#include #include #include #include @@ -62,17 +63,17 @@ void test_binary_operation_for_bitsize(Operation &op) for (size_t i = 0; i * chunk_bits < Bits; i++) { if ((chunk_type)(iresult >> (i * chunk_bits)) != vresult.data[i]) { std::printf("Test failure:\n"); - std::printf("Bits: %i\n", Bits); - std::printf("a: %016lx\n", ia); - std::printf("b: %016lx\n", ib); - std::printf("iresult: %016lx\n", iresult); - std::printf("vresult: %016lx\n", vresult.template get()); + std::printf("Bits: %zu\n", Bits); + std::printf("a: %016" PRIx64 "\n", ia); + std::printf("b: %016" PRIx64 "\n", ib); + std::printf("iresult: %016" PRIx64 "\n", iresult); + std::printf("vresult: %016" PRIx64 "\n", vresult.template get()); std::terminate(); } } } - std::printf("Test passed @ Bits = %i.\n", Bits); + std::printf("Test passed @ Bits = %zu.\n", Bits); } template From a55e8594b7a70fc84d0bc6dd1e3075b2737daaab Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 12 Jun 2024 00:17:25 +0000 Subject: [PATCH 10/37] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 92fce6c7d..87f8f17f9 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LIBS += -lrt endif endif -YOSYS_VER := 0.42+10 +YOSYS_VER := 0.42+12 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 3ed2865ac5a251e89b6ef3ca86d4cdc50f2256e2 Mon Sep 17 00:00:00 2001 From: Asherah Connor Date: Fri, 7 Jun 2024 14:30:46 +0300 Subject: [PATCH 11/37] cxxrtl: capi: don't use deprecated invocation. --- backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc b/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc index 3c62401dd..34801c2d1 100644 --- a/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc +++ b/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc @@ -47,7 +47,7 @@ cxxrtl_handle cxxrtl_create_at(cxxrtl_toplevel design, const char *top_path_) { cxxrtl_handle handle = new _cxxrtl_handle; handle->module = std::move(design->module); - handle->module->debug_info(handle->objects, top_path); + handle->module->debug_info(&handle->objects, nullptr, top_path); delete design; return handle; } From 62bff3a20436ee547a500e27e6cc6b7f550a6013 Mon Sep 17 00:00:00 2001 From: Asherah Connor Date: Fri, 7 Jun 2024 14:31:13 +0300 Subject: [PATCH 12/37] cxxrtl: don't need to specify a value for "path". Callers of the deprecated method had a path already. --- backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h index 70f30e7f9..d1d6bd8dc 100644 --- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h +++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h @@ -1582,7 +1582,7 @@ struct module { // Compatibility method. #if __has_attribute(deprecated) - __attribute__((deprecated("Use `debug_info(&items, /*scopes=*/nullptr, path);` instead. (`path` could be \"top \".)"))) + __attribute__((deprecated("Use `debug_info(&items, /*scopes=*/nullptr, path);` instead."))) #endif void debug_info(debug_items &items, std::string path) { debug_info(&items, /*scopes=*/nullptr, path); From 2fd2b6538df31f345ac1378b3185ff8785f5684e Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Fri, 14 Jun 2024 00:17:13 +0000 Subject: [PATCH 13/37] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 87f8f17f9..7760cec43 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LIBS += -lrt endif endif -YOSYS_VER := 0.42+12 +YOSYS_VER := 0.42+15 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 2f0f10cb871228248c8e012a9d6756c1e1b972c1 Mon Sep 17 00:00:00 2001 From: Philippe Sauter Date: Fri, 14 Jun 2024 15:30:03 +0200 Subject: [PATCH 14/37] peepopt: limit padding from shiftadd The input to a shift operation is padded. This reduced the final number of MUX cells but during techmap it can create huge temporary multiplexers in the log shifter. This significantly increases runtime and resources. A limit is added with a warning when it is used. --- passes/pmgen/peepopt.cc | 11 +++++++++++ passes/pmgen/peepopt_shiftadd.pmg | 15 ++++++++++++--- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc index edd3b18a8..5638ec3c2 100644 --- a/passes/pmgen/peepopt.cc +++ b/passes/pmgen/peepopt.cc @@ -25,6 +25,9 @@ PRIVATE_NAMESPACE_BEGIN bool did_something; +// scratchpad configurations for pmgen +int shiftadd_max_ratio; + #include "passes/pmgen/peepopt_pm.h" struct PeepoptPass : public Pass { @@ -50,6 +53,9 @@ struct PeepoptPass : public Pass { log("\n"); log(" * shiftadd - Replace A>>(B+D) with (A'>>D)>>(B) where D is constant and\n"); log(" A' is derived from A by padding or cutting inaccessible bits.\n"); + log(" Scratchpad: 'peepopt.shiftadd.max_data_multiple' (default: 2)\n"); + log(" limits the amount of padding to a multiple of the data, \n"); + log(" to avoid high resource usage from large temporary MUX trees.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) override @@ -63,6 +69,11 @@ struct PeepoptPass : public Pass { } extra_args(args, argidx, design); + // limit the padding from shiftadd to a multiple of the input data + // during techmap it creates (#data + #padding) * log(shift) $_MUX_ cells + // 2x implies there is a constant shift larger than the input-data which should be extremely rare + shiftadd_max_ratio = design->scratchpad_get_int("peepopt.shiftadd.max_data_multiple", 2); + for (auto module : design->selected_modules()) { did_something = true; diff --git a/passes/pmgen/peepopt_shiftadd.pmg b/passes/pmgen/peepopt_shiftadd.pmg index e690ff651..62f54efe5 100644 --- a/passes/pmgen/peepopt_shiftadd.pmg +++ b/passes/pmgen/peepopt_shiftadd.pmg @@ -91,11 +91,21 @@ code // it should only differ if previous passes create invalid data log_assert(!(offset>0 && var_signed)); + SigSpec old_a = port(shift, \A); // data + std::string location = shift->get_src_attribute(); + + if(shiftadd_max_ratio>0 && offset<0 && -offset*shiftadd_max_ratio > old_a.size()) { + log_warning("at %s: candiate for shiftadd optimization (shifting '%s' by '%s - %d' bits) " + "was ignored to avoid high resource usage, see help peepopt\n", + location.c_str(), log_signal(old_a), log_signal(var_signal), -offset); + reject; + } + did_something = true; log("shiftadd pattern in %s: shift=%s, add/sub=%s, offset: %d\n", \ log_id(module), log_id(shift), log_id(add), offset); - SigSpec old_a = port(shift, \A), new_a; + SigSpec new_a; if(offset<0) { // data >> (...-c) transformed to {data, c'X} >> (...) SigSpec padding( (shift->type.in($shiftx) ? State::Sx : State::S0), -offset ); @@ -107,14 +117,13 @@ code new_a.append(old_a.extract_end(offset)); } else { // warn user in case data is empty (no bits left) - std::string location = shift->get_src_attribute(); if (location.empty()) location = shift->name.str(); if(shift->type.in($shiftx)) log_warning("at %s: result of indexed part-selection is always constant (selecting from '%s' with index '%s + %d')\n", \ location.c_str(), log_signal(old_a), log_signal(var_signal), offset); else - log_warning("at %s: result of shift operation is always constant (shifting '%s' by '%s + %d'-bits)\n", \ + log_warning("at %s: result of shift operation is always constant (shifting '%s' by '%s + %d' bits)\n", \ location.c_str(), log_signal(old_a), log_signal(var_signal), offset); } } From 54bf9ccf0684cb4fcb8811db43a966c99da975e8 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 21 May 2024 17:08:07 +0200 Subject: [PATCH 15/37] Add initial support for Verific without additional YosysHQ patch --- Makefile | 11 +++++- frontends/verific/verific.cc | 76 ++++++++++++++++++++++++++++++++++-- 2 files changed, 83 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 7760cec43..7091318ca 100644 --- a/Makefile +++ b/Makefile @@ -21,6 +21,7 @@ ENABLE_VERIFIC_EDIF := 0 ENABLE_VERIFIC_LIBERTY := 0 DISABLE_VERIFIC_EXTENSIONS := 0 DISABLE_VERIFIC_VHDL := 0 +DISABLE_VERIFIC_HIER_TREE := 0 ENABLE_COVER := 1 ENABLE_LIBYOSYS := 0 ENABLE_ZLIB := 1 @@ -471,7 +472,15 @@ endif LIBS_VERIFIC = ifeq ($(ENABLE_VERIFIC),1) VERIFIC_DIR ?= /usr/local/src/verific_lib -VERIFIC_COMPONENTS ?= verilog database util containers hier_tree +VERIFIC_COMPONENTS ?= verilog database util containers +ifneq ($(DISABLE_VERIFIC_HIER_TREE),1) +VERIFIC_COMPONENTS += hier_tree +CXXFLAGS += -DVERIFIC_HIER_TREE_SUPPORT +else +ifneq ($(wildcard $(VERIFIC_DIR)/hier_tree),) +VERIFIC_COMPONENTS += hier_tree +endif +endif ifneq ($(DISABLE_VERIFIC_VHDL),1) VERIFIC_COMPONENTS += vhdl CXXFLAGS += -DVERIFIC_VHDL_SUPPORT diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index f7c2cefd2..5c0759567 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -43,7 +43,9 @@ USING_YOSYS_NAMESPACE #endif #include "veri_file.h" +#ifdef VERIFIC_HIER_TREE_SUPPORT #include "hier_tree.h" +#endif #include "VeriModule.h" #include "VeriWrite.h" #include "VeriLibrary.h" @@ -72,12 +74,16 @@ USING_YOSYS_NAMESPACE #endif #ifndef YOSYSHQ_VERIFIC_API_VERSION -# error "Only YosysHQ flavored Verific is supported. Please contact office@yosyshq.com for commercial support for Yosys+Verific." -#endif - +#warning "Only YosysHQ flavored Verific is fully supported. Please contact office@yosyshq.com for commercial support for Yosys+Verific." +#else #if YOSYSHQ_VERIFIC_API_VERSION < 20230901 # error "Please update your version of YosysHQ flavored Verific." #endif +#endif + +#ifndef DB_PRESERVE_INITIAL_VALUE +#error "Verific must have DB_PRESERVE_INITIAL_VALUE compile flag set on" +#endif #ifdef __clang__ #pragma clang diagnostic pop @@ -115,9 +121,15 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil if (log_verific_callback) { string full_message = stringf("%s%s\n", message_prefix.c_str(), message.c_str()); +#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), linefile ? linefile->GetLeftLine() : 0, linefile ? linefile->GetLeftCol() : 0, linefile ? linefile->GetRightLine() : 0, linefile ? linefile->GetRightCol() : 0, full_message.c_str()); +#else + log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), + linefile ? LineFile::GetLineNo(linefile) : 0, 0, + linefile ? LineFile::GetLineNo(linefile) : 0, 0, full_message.c_str()); +#endif } else { if (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_WARNING || msg_type == VERIFIC_PROGRAM_ERROR) log_warning_noprefix("%s%s\n", message_prefix.c_str(), message.c_str()); @@ -392,6 +404,7 @@ static const RTLIL::Const verific_const(const char* type_name, const char *value return extract_verilog_const(value, allow_string, output_signed); } +#ifdef YOSYSHQ_VERIFIC_API_VERSION static const std::string verific_unescape(const char *value) { std::string val = std::string(value); @@ -399,6 +412,7 @@ static const std::string verific_unescape(const char *value) return val.substr(1,val.size()-2); return value; } +#endif void VerificImporter::import_attributes(dict &attributes, DesignObj *obj, Netlist *nl) { @@ -408,8 +422,13 @@ void VerificImporter::import_attributes(dict &att MapIter mi; Att *attr; +#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS if (obj->Linefile()) attributes[ID::src] = stringf("%s:%d.%d-%d.%d", LineFile::GetFileName(obj->Linefile()), obj->Linefile()->GetLeftLine(), obj->Linefile()->GetLeftCol(), obj->Linefile()->GetRightLine(), obj->Linefile()->GetRightCol()); +#else + if (obj->Linefile()) + attributes[ID::src] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile())); +#endif FOREACH_ATTRIBUTE(obj, mi, attr) { if (attr->Key()[0] == ' ' || attr->Value() == nullptr) @@ -1265,6 +1284,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr return true; } +#ifdef YOSYSHQ_VERIFIC_API_VERSION if (inst->Type() == OPER_YOSYSHQ_SET_TAG) { RTLIL::SigSpec sig_expr = operatorInport(inst, "expr"); @@ -1301,6 +1321,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr module->connect(operatorOutput(inst),module->FutureFF(new_verific_id(inst), operatorInput(inst))); return true; } +#endif #undef IN #undef IN1 @@ -2067,6 +2088,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma continue; } +#ifdef YOSYSHQ_VERIFIC_API_VERSION if (inst->Type() == PRIM_YOSYSHQ_INITSTATE) { if (verific_verbose) @@ -2078,6 +2100,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma if (!mode_keep) continue; } +#endif if (!mode_keep && verific_sva_prims.count(inst->Type())) { if (verific_verbose) @@ -2680,7 +2703,24 @@ std::string verific_import(Design *design, const std::mapGetLibrary("work"); + FOREACH_CELL_OF_LIBRARY(l,mi,c) { + MapIter ni ; + Netlist *nl; + FOREACH_NETLIST_OF_CELL(c, ni, nl) { + if (nl) + nl_todo.emplace(nl->CellBaseName(), nl); + } + } +#endif } else { @@ -2737,7 +2777,11 @@ std::string verific_import(Design *design, const std::mapCellBaseName(), nl); delete netlists; +#else + if (parameters.Size()) + log_warning("Please note that parameters are not propagated during import.\n"); + veri_file::ElaborateAll(work.c_str()); + + MapIter mi ; + Verific::Cell *c ; + Library *l = Libset::Global()->GetLibrary(work.c_str()); + FOREACH_CELL_OF_LIBRARY(l,mi,c) { + MapIter ni ; + Netlist *nl; + FOREACH_NETLIST_OF_CELL(c, ni, nl) { + if (nl) + nl_todo.emplace(nl->CellBaseName(), nl); + } + } +#endif } else { @@ -3949,7 +4013,11 @@ struct VerificPass : public Pass { } log("Running hier_tree::Elaborate().\n"); +#ifdef VERIFIC_HIER_TREE_SUPPORT netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, ¶meters); +#else + netlists = veri_file::ElaborateMultipleTop(&veri_modules, ¶meters); +#endif } Netlist *nl; @@ -4026,7 +4094,9 @@ struct VerificPass : public Pass { #ifdef YOSYSHQ_VERIFIC_EXTENSIONS VerificExtensions::Reset(); #endif +#ifdef VERIFIC_HIER_TREE_SUPPORT hier_tree::DeleteHierarchicalTree(); +#endif veri_file::Reset(); #ifdef VERIFIC_VHDL_SUPPORT vhdl_file::Reset(); From 25d50bb2afd8d39409d697946057772545e9c5e3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 7 Jun 2024 14:58:33 +0200 Subject: [PATCH 16/37] VHDL only build support --- Makefile | 11 ++- frontends/verific/verific.cc | 156 ++++++++++++++++++++++++++------ frontends/verific/verificsva.cc | 6 +- 3 files changed, 144 insertions(+), 29 deletions(-) diff --git a/Makefile b/Makefile index 7091318ca..0712e987b 100644 --- a/Makefile +++ b/Makefile @@ -20,6 +20,7 @@ ENABLE_VERIFIC := 0 ENABLE_VERIFIC_EDIF := 0 ENABLE_VERIFIC_LIBERTY := 0 DISABLE_VERIFIC_EXTENSIONS := 0 +DISABLE_VERIFIC_SYSTEMVERILOG := 0 DISABLE_VERIFIC_VHDL := 0 DISABLE_VERIFIC_HIER_TREE := 0 ENABLE_COVER := 1 @@ -472,7 +473,7 @@ endif LIBS_VERIFIC = ifeq ($(ENABLE_VERIFIC),1) VERIFIC_DIR ?= /usr/local/src/verific_lib -VERIFIC_COMPONENTS ?= verilog database util containers +VERIFIC_COMPONENTS ?= database util containers ifneq ($(DISABLE_VERIFIC_HIER_TREE),1) VERIFIC_COMPONENTS += hier_tree CXXFLAGS += -DVERIFIC_HIER_TREE_SUPPORT @@ -481,6 +482,14 @@ ifneq ($(wildcard $(VERIFIC_DIR)/hier_tree),) VERIFIC_COMPONENTS += hier_tree endif endif +ifneq ($(DISABLE_VERIFIC_SYSTEMVERILOG),1) +VERIFIC_COMPONENTS += verilog +CXXFLAGS += -DVERIFIC_SYSTEMVERILOG_SUPPORT +else +ifneq ($(wildcard $(VERIFIC_DIR)/verilog),) +VERIFIC_COMPONENTS += verilog +endif +endif ifneq ($(DISABLE_VERIFIC_VHDL),1) VERIFIC_COMPONENTS += vhdl CXXFLAGS += -DVERIFIC_VHDL_SUPPORT diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 5c0759567..c76ee14e5 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -42,14 +42,17 @@ USING_YOSYS_NAMESPACE #pragma clang diagnostic ignored "-Woverloaded-virtual" #endif -#include "veri_file.h" #ifdef VERIFIC_HIER_TREE_SUPPORT #include "hier_tree.h" #endif + +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT +#include "veri_file.h" #include "VeriModule.h" #include "VeriWrite.h" #include "VeriLibrary.h" #include "VeriExpression.h" +#endif #ifdef VERIFIC_VHDL_SUPPORT #include "vhdl_file.h" @@ -103,7 +106,9 @@ bool verific_import_pending; string verific_error_msg; int verific_sva_fsm_limit; +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT vector verific_incdirs, verific_libdirs, verific_libexts; +#endif void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefile, const char *msg, va_list args) { @@ -157,6 +162,7 @@ string get_full_netlist_name(Netlist *nl) return nl->CellBaseName(); } +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT class YosysStreamCallBackHandler : public VerificStreamCallBackHandler { public: @@ -186,6 +192,7 @@ public: }; YosysStreamCallBackHandler verific_read_cb; +#endif // ================================================================== @@ -1825,10 +1832,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma for (auto net : anyseq_nets) module->connect(net_map_at(net), module->Anyseq(new_verific_id(net))); +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT pool sva_asserts; pool sva_assumes; pool sva_covers; pool sva_triggers; +#endif pool past_ffs; @@ -1945,6 +1954,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma continue; } +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (inst->Type() == PRIM_SVA_ASSERT || inst->Type() == PRIM_SVA_IMMEDIATE_ASSERT) sva_asserts.insert(inst); @@ -2087,6 +2097,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma if (!mode_keep) continue; } +#endif #ifdef YOSYSHQ_VERIFIC_API_VERSION if (inst->Type() == PRIM_YOSYSHQ_INITSTATE) @@ -2210,6 +2221,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma } } +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (!mode_nosva) { for (auto inst : sva_asserts) { @@ -2229,6 +2241,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma merge_past_ffs(past_ffs); } +#endif if (!mode_fullinit) { @@ -2280,7 +2293,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma // ================================================================== -VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_at_only) +VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_at_only YS_MAYBE_UNUSED) { module = importer->module; @@ -2289,6 +2302,7 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a Instance *inst = net->Driver(); +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT // Detect condition expression in sva_at_only mode if (sva_at_only) do { @@ -2337,7 +2351,7 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a net = inst->GetInput(); inst = net->Driver();; } - +#endif if (inst != nullptr && inst->Type() == PRIM_INV) { net = inst->GetInput(); @@ -2383,6 +2397,7 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a inst = net->Driver();; } while (0); +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT // Detect condition expression do { if (body_net == nullptr) @@ -2407,6 +2422,7 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a cond_net = inst_mux->GetControl(); cond_pol = pwr1; } while (0); +#endif clock_net = net; clock_sig = importer->net_map_at(clock_net); @@ -2683,15 +2699,16 @@ std::string verific_import(Design *design, const std::map nl_todo, nl_done; - - VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1); Array *netlists = NULL; Array veri_libs, vhdl_libs; #ifdef VERIFIC_VHDL_SUPPORT VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1); if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib); #endif +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT + VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1); if (veri_lib) veri_libs.InsertLast(veri_lib); +#endif Map verific_params(STRING_HASH); for (const auto &i : parameters) @@ -2708,7 +2725,13 @@ std::string verific_import(Design *design, const std::mapGetLibrary("work"); @@ -2717,7 +2740,7 @@ std::string verific_import(Design *design, const std::mapCellBaseName(), nl); + netlists->InsertLast(nl); } } #endif @@ -2728,7 +2751,8 @@ std::string verific_import(Design *design, const std::map= 0; static_elaborate--) #endif { - Array veri_modules, vhdl_units; +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT + Array veri_modules; if (veri_lib) { VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1); @@ -2760,8 +2784,10 @@ std::string verific_import(Design *design, const std::mapGetPrimUnit(top.c_str()); if (vhdl_unit) @@ -2780,7 +2806,17 @@ std::string verific_import(Design *design, const std::mapInsertLast(Netlist::PresentDesign()); +#else + // Both SystemVerilog and VHDL support +#endif #endif } } @@ -2828,7 +2864,9 @@ std::string verific_import(Design *design, const std::map..\n"); log("\n"); log("Load the specified Verilog/SystemVerilog files into Verific.\n"); @@ -2893,6 +2934,7 @@ struct VerificPass : public Pass { log("Like -sv, but define FORMAL instead of SYNTHESIS.\n"); log("\n"); log("\n"); +#endif #ifdef VERIFIC_VHDL_SUPPORT log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl2019|-vhdl} ..\n"); log("\n"); @@ -2919,6 +2961,7 @@ struct VerificPass : public Pass { log("\n"); log("\n"); #endif +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT log(" verific {-f|-F} [-vlog95|-vlog2k|-sv2005|-sv2009|\n"); log(" -sv2012|-sv|-formal] \n"); log("\n"); @@ -2952,6 +2995,7 @@ struct VerificPass : public Pass { log(" -sverilog\n"); log("\n"); log("\n"); +#endif log(" verific [-work ] {-sv|-vhdl|...} \n"); log("\n"); log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n"); @@ -2964,6 +3008,7 @@ struct VerificPass : public Pass { log("(-L may be used more than once)\n"); log("\n"); log("\n"); +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT log(" verific -vlog-incdir ..\n"); log("\n"); log("Add Verilog include directories.\n"); @@ -2990,6 +3035,7 @@ struct VerificPass : public Pass { log("Remove Verilog defines previously set with -vlog-define.\n"); log("\n"); log("\n"); +#endif log(" verific -set-error ..\n"); log(" verific -set-warning ..\n"); log(" verific -set-info ..\n"); @@ -3024,9 +3070,11 @@ struct VerificPass : public Pass { log(" -no-split-complex-ports\n"); log(" Complex ports (structs or arrays) are not split and remain packed as a single port.\n"); log("\n"); +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT log(" -autocover\n"); log(" Generate automatic cover statements for all asserts\n"); log("\n"); +#endif log(" -fullinit\n"); log(" Keep all register initializations, even those for non-FF registers.\n"); log("\n"); @@ -3059,12 +3107,14 @@ struct VerificPass : public Pass { log(" -V\n"); log(" Import Verific netlist as-is without translating to Yosys cell types. \n"); log("\n"); +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT log(" -nosva\n"); log(" Ignore SVA properties, do not infer checker logic.\n"); log("\n"); log(" -L \n"); log(" Maximum number of ctrl bits for SVA checker FSMs (default=16).\n"); log("\n"); +#endif log(" -n\n"); log(" Keep all Verific names on instances and nets. By default only\n"); log(" user-declared names are preserved.\n"); @@ -3188,7 +3238,7 @@ struct VerificPass : public Pass { #endif msg_type_t prev_1063; - +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT void add_modules_to_map(Map &map, std::string work, bool flag_lib) { MapIter mi ; @@ -3222,6 +3272,7 @@ struct VerificPass : public Pass { if (Message::GetMessageType("VERI-1063")!=prev_1063) Message::SetMessageType("VERI-1063", prev_1063); } +#endif void execute(std::vector args, RTLIL::Design *design) override { @@ -3254,10 +3305,11 @@ struct VerificPass : public Pass { // Properly respect order of read and write for rams RuntimeFlags::SetVar("db_change_inplace_ram_blocking_write_before_read", 1); +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1); - +#endif #ifdef VERIFIC_VHDL_SUPPORT RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0); RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1); @@ -3270,6 +3322,7 @@ struct VerificPass : public Pass { //RuntimeFlags::SetVar("vhdl_preserve_comments", 1); RuntimeFlags::SetVar("vhdl_preserve_drivers", 1); #endif +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT RuntimeFlags::SetVar("veri_preserve_assignments", 1); RuntimeFlags::SetVar("veri_preserve_comments", 1); RuntimeFlags::SetVar("veri_preserve_drivers", 1); @@ -3282,7 +3335,7 @@ struct VerificPass : public Pass { // https://github.com/YosysHQ/yosys/issues/1055 RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ; - +#endif RuntimeFlags::SetVar("verific_produce_verbose_syntax_error_message", 1); #ifndef DB_PRESERVE_INITIAL_VALUE @@ -3312,8 +3365,9 @@ struct VerificPass : public Pass { std::string work = "work"; bool is_work_set = false; (void)is_work_set; +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT veri_file::RegisterCallBackVerificStream(&verific_read_cb); - +#endif if (GetSize(args) > argidx && (args[argidx] == "-set-error" || args[argidx] == "-set-warning" || args[argidx] == "-set-info" || args[argidx] == "-set-ignore")) { @@ -3347,6 +3401,7 @@ struct VerificPass : public Pass { goto check_error; } +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (GetSize(args) > argidx && args[argidx] == "-vlog-incdir") { for (argidx++; argidx < GetSize(args); argidx++) verific_incdirs.push_back(args[argidx]); @@ -3566,14 +3621,17 @@ struct VerificPass : public Pass { verific_import_pending = true; goto check_error; } +#endif #ifdef VERIFIC_VHDL_SUPPORT if (GetSize(args) > argidx && args[argidx] == "-vhdl87") { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str()); bool flag_lib = false; - for (argidx++; argidx < GetSize(args); argidx++) { + argidx++; + while (argidx < GetSize(args)) { if (args[argidx] == "-lib") { flag_lib = true; + argidx++; continue; } if (args[argidx].compare(0, 1, "-") == 0) { @@ -3594,9 +3652,11 @@ struct VerificPass : public Pass { if (GetSize(args) > argidx && args[argidx] == "-vhdl93") { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str()); bool flag_lib = false; - for (argidx++; argidx < GetSize(args); argidx++) { + argidx++; + while (argidx < GetSize(args)) { if (args[argidx] == "-lib") { flag_lib = true; + argidx++; continue; } if (args[argidx].compare(0, 1, "-") == 0) { @@ -3617,9 +3677,11 @@ struct VerificPass : public Pass { if (GetSize(args) > argidx && args[argidx] == "-vhdl2k") { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str()); bool flag_lib = false; - for (argidx++; argidx < GetSize(args); argidx++) { + argidx++; + while (argidx < GetSize(args)) { if (args[argidx] == "-lib") { flag_lib = true; + argidx++; continue; } if (args[argidx].compare(0, 1, "-") == 0) { @@ -3640,9 +3702,11 @@ struct VerificPass : public Pass { if (GetSize(args) > argidx && (args[argidx] == "-vhdl2019")) { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2019").c_str()); bool flag_lib = false; - for (argidx++; argidx < GetSize(args); argidx++) { + argidx++; + while (argidx < GetSize(args)) { if (args[argidx] == "-lib") { flag_lib = true; + argidx++; continue; } if (args[argidx].compare(0, 1, "-") == 0) { @@ -3663,9 +3727,11 @@ struct VerificPass : public Pass { if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str()); bool flag_lib = false; - for (argidx++; argidx < GetSize(args); argidx++) { + argidx++; + while (argidx < GetSize(args)) { if (args[argidx] == "-lib") { flag_lib = true; + argidx++; continue; } if (args[argidx].compare(0, 1, "-") == 0) { @@ -3774,8 +3840,10 @@ struct VerificPass : public Pass { #else goto check_error; #endif +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT else veri_file::PrettyPrint(filename, module, work.c_str()); +#endif goto check_error; } @@ -3816,6 +3884,7 @@ struct VerificPass : public Pass { mode_keep = true; continue; } +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (args[argidx] == "-nosva") { mode_nosva = true; continue; @@ -3824,14 +3893,17 @@ struct VerificPass : public Pass { verific_sva_fsm_limit = atoi(args[++argidx].c_str()); continue; } +#endif if (args[argidx] == "-n") { mode_names = true; continue; } +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (args[argidx] == "-autocover") { mode_autocover = true; continue; } +#endif if (args[argidx] == "-fullinit") { mode_fullinit = true; continue; @@ -3884,19 +3956,22 @@ struct VerificPass : public Pass { VerificExtensions::ElaborateAndRewrite(work, ¶meters); verific_error_msg.clear(); #endif +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (!ppfile.empty()) veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str()); - +#endif log("Running hier_tree::ElaborateAll().\n"); - VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1); - - Array veri_libs, vhdl_libs; #ifdef VERIFIC_VHDL_SUPPORT + Array vhdl_libs; VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib); #endif +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT + Array veri_libs; + VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1); if (veri_lib) veri_libs.InsertLast(veri_lib); +#endif #ifdef VERIFIC_HIER_TREE_SUPPORT Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, ¶meters); @@ -3909,8 +3984,12 @@ struct VerificPass : public Pass { #else if (parameters.Size()) log_warning("Please note that parameters are not propagated during import.\n"); +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT veri_file::ElaborateAll(work.c_str()); - +#endif +#ifdef VERIFIC_VHDL_SUPPORT + vhdl_file::ElaborateAll(work.c_str()); +#endif MapIter mi ; Verific::Cell *c ; Library *l = Libset::Global()->GetLibrary(work.c_str()); @@ -3936,17 +4015,20 @@ struct VerificPass : public Pass { #endif { - VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1); #ifdef VERIFIC_VHDL_SUPPORT + Array vhdl_units; VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); #endif - - Array veri_modules, vhdl_units; +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT + Array veri_modules; + VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1); +#endif for (int i = argidx; i < GetSize(args); i++) { const char *name = args[i].c_str(); top_mod_names.insert(name); +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr; if (veri_module) { if (veri_module->IsConfiguration()) { @@ -3974,6 +4056,7 @@ struct VerificPass : public Pass { } continue; } +#endif #ifdef VERIFIC_VHDL_SUPPORT VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr; if (vhdl_unit) { @@ -3990,13 +4073,15 @@ struct VerificPass : public Pass { VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, ¶meters); verific_error_msg.clear(); #endif +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (!ppfile.empty()) veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str()); - +#endif #ifdef YOSYSHQ_VERIFIC_EXTENSIONS continue; } #endif +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT const char *lib_name = nullptr; SetIter si; FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) { @@ -4011,12 +4096,24 @@ struct VerificPass : public Pass { } } } - +#endif log("Running hier_tree::Elaborate().\n"); #ifdef VERIFIC_HIER_TREE_SUPPORT netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, ¶meters); #else +#if defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && !defined(VERIFIC_VHDL_SUPPORT) + // SystemVerilog support only netlists = veri_file::ElaborateMultipleTop(&veri_modules, ¶meters); +#elif defined(VERIFIC_VHDL_SUPPORT) && !defined(VERIFIC_SYSTEMVERILOG_SUPPORT) + // VHDL support only + netlists = new Array(top_mod_names.size()); + for (auto &name : top_mod_names) { + vhdl_file::Elaborate(name.c_str(), work.c_str(), 0, ¶meters); + netlists->InsertLast(Netlist::PresentDesign()); + } +#else + // Both SystemVerilog and VHDL support +#endif #endif } @@ -4074,11 +4171,12 @@ struct VerificPass : public Pass { nl.second->ChangePortBusStructures(1 /* hierarchical */); } +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (!dumpfile.empty()) { VeriWrite veri_writer; veri_writer.WriteFile(dumpfile.c_str(), Netlist::PresentDesign()); } - +#endif while (!nl_todo.empty()) { auto it = nl_todo.begin(); Netlist *nl = it->second; @@ -4097,7 +4195,9 @@ struct VerificPass : public Pass { #ifdef VERIFIC_HIER_TREE_SUPPORT hier_tree::DeleteHierarchicalTree(); #endif +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT veri_file::Reset(); +#endif #ifdef VERIFIC_VHDL_SUPPORT vhdl_file::Reset(); #endif @@ -4111,9 +4211,11 @@ struct VerificPass : public Pass { Message::Reset(); RuntimeFlags::DeleteAllFlags(); LineFile::DeleteAllLineFiles(); +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT verific_incdirs.clear(); verific_libdirs.clear(); verific_libexts.clear(); +#endif verific_import_pending = false; goto check_error; } diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc index 222c7d2e9..b219c0165 100644 --- a/frontends/verific/verificsva.cc +++ b/frontends/verific/verificsva.cc @@ -80,6 +80,7 @@ USING_YOSYS_NAMESPACE using namespace Verific; #endif +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT PRIVATE_NAMESPACE_BEGIN // Non-deterministic FSM @@ -1878,5 +1879,8 @@ bool verific_is_sva_net(VerificImporter *importer, Verific::Net *net) worker.importer = importer; return worker.net_to_ast_driver(net) != nullptr; } - +#else +YOSYS_NAMESPACE_BEGIN +pool verific_sva_prims = {}; +#endif YOSYS_NAMESPACE_END From 7bec332b68e2c72457e90ed4dbf0cb56ad350f42 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 10 Jun 2024 09:44:39 +0200 Subject: [PATCH 17/37] SV + VHDL with RTL support --- frontends/verific/verific.cc | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index c76ee14e5..84fc834ea 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2816,6 +2816,14 @@ std::string verific_import(Design *design, const std::mapInsertLast(Netlist::PresentDesign()); #else // Both SystemVerilog and VHDL support + if (veri_modules.Size()>0) + netlists = veri_file::ElaborateMultipleTop(&veri_modules, &verific_params); + else + netlists = new Array(1); + if (vhdl_units.Size()>0) { + vhdl_file::Elaborate(top.c_str(), "work", 0, &verific_params); + netlists->InsertLast(Netlist::PresentDesign()); + } #endif #endif } @@ -4113,6 +4121,16 @@ struct VerificPass : public Pass { } #else // Both SystemVerilog and VHDL support + if (veri_modules.Size()>0) + netlists = veri_file::ElaborateMultipleTop(&veri_modules, ¶meters); + else + netlists = new Array(1); + if (vhdl_units.Size()>0) { + for (auto &name : top_mod_names) { + vhdl_file::Elaborate(name.c_str(), work.c_str(), 0, ¶meters); + netlists->InsertLast(Netlist::PresentDesign()); + } + } #endif #endif } From e2e189647f36dd3609711c233d6febebf2a7a8f3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 10 Jun 2024 10:12:33 +0200 Subject: [PATCH 18/37] Cleanup --- frontends/verific/verific.cc | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 84fc834ea..0c575685f 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -84,10 +84,6 @@ USING_YOSYS_NAMESPACE #endif #endif -#ifndef DB_PRESERVE_INITIAL_VALUE -#error "Verific must have DB_PRESERVE_INITIAL_VALUE compile flag set on" -#endif - #ifdef __clang__ #pragma clang diagnostic pop #endif @@ -2700,12 +2696,13 @@ std::string verific_import(Design *design, const std::map nl_todo, nl_done; Array *netlists = NULL; - Array veri_libs, vhdl_libs; #ifdef VERIFIC_VHDL_SUPPORT + Array vhdl_libs; VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1); if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib); #endif #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT + Array veri_libs; VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1); if (veri_lib) veri_libs.InsertLast(veri_lib); #endif @@ -3901,17 +3898,15 @@ struct VerificPass : public Pass { verific_sva_fsm_limit = atoi(args[++argidx].c_str()); continue; } -#endif - if (args[argidx] == "-n") { - mode_names = true; - continue; - } -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (args[argidx] == "-autocover") { mode_autocover = true; continue; } #endif + if (args[argidx] == "-n") { + mode_names = true; + continue; + } if (args[argidx] == "-fullinit") { mode_fullinit = true; continue; From 7c3094633d7f928909984127be875dfa33ba60b5 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 11 Jun 2024 07:48:26 +0200 Subject: [PATCH 19/37] Compile with hier_tree separate SV and VHDL as well --- frontends/verific/verific.cc | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 0c575685f..39e968837 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2696,13 +2696,13 @@ std::string verific_import(Design *design, const std::map nl_todo, nl_done; Array *netlists = NULL; -#ifdef VERIFIC_VHDL_SUPPORT Array vhdl_libs; +#ifdef VERIFIC_VHDL_SUPPORT VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1); if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib); #endif -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT Array veri_libs; +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1); if (veri_lib) veri_libs.InsertLast(veri_lib); #endif @@ -2748,9 +2748,8 @@ std::string verific_import(Design *design, const std::map= 0; static_elaborate--) #endif { -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT Array veri_modules; - +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (veri_lib) { VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1); if (veri_module) { @@ -2783,8 +2782,8 @@ std::string verific_import(Design *design, const std::mapGetPrimUnit(top.c_str()); if (vhdl_unit) @@ -3965,13 +3964,13 @@ struct VerificPass : public Pass { #endif log("Running hier_tree::ElaborateAll().\n"); -#ifdef VERIFIC_VHDL_SUPPORT Array vhdl_libs; +#ifdef VERIFIC_VHDL_SUPPORT VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib); #endif -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT Array veri_libs; +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1); if (veri_lib) veri_libs.InsertLast(veri_lib); #endif @@ -4018,12 +4017,12 @@ struct VerificPass : public Pass { #endif { -#ifdef VERIFIC_VHDL_SUPPORT Array vhdl_units; +#ifdef VERIFIC_VHDL_SUPPORT VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); #endif -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT Array veri_modules; +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1); #endif for (int i = argidx; i < GetSize(args); i++) From 0a81c8e161cd6abb36e3ba4eb5edfc745836a9d5 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 11 Jun 2024 08:26:16 +0200 Subject: [PATCH 20/37] Import all modules from all libraries when when needed --- frontends/verific/verific.cc | 36 ++++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 39e968837..e7bc24219 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2731,13 +2731,17 @@ std::string verific_import(Design *design, const std::mapGetLibrary("work"); - FOREACH_CELL_OF_LIBRARY(l,mi,c) { - MapIter ni ; - Netlist *nl; - FOREACH_NETLIST_OF_CELL(c, ni, nl) { - if (nl) - netlists->InsertLast(nl); + MapIter it ; + Library *l ; + FOREACH_LIBRARY_OF_LIBSET(Libset::Global(),it,l) { + if (l == Library::Primitives() || l == Library::Operators()) continue; + FOREACH_CELL_OF_LIBRARY(l,mi,c) { + MapIter ni ; + Netlist *nl; + FOREACH_NETLIST_OF_CELL(c, ni, nl) { + if (nl) + netlists->InsertLast(nl); + } } } #endif @@ -3994,13 +3998,17 @@ struct VerificPass : public Pass { #endif MapIter mi ; Verific::Cell *c ; - Library *l = Libset::Global()->GetLibrary(work.c_str()); - FOREACH_CELL_OF_LIBRARY(l,mi,c) { - MapIter ni ; - Netlist *nl; - FOREACH_NETLIST_OF_CELL(c, ni, nl) { - if (nl) - nl_todo.emplace(nl->CellBaseName(), nl); + MapIter it ; + Library *l ; + FOREACH_LIBRARY_OF_LIBSET(Libset::Global(),it,l) { + if (l == Library::Primitives() || l == Library::Operators()) continue; + FOREACH_CELL_OF_LIBRARY(l,mi,c) { + MapIter ni ; + Netlist *nl; + FOREACH_NETLIST_OF_CELL(c, ni, nl) { + if (nl) + nl_todo.emplace(nl->CellBaseName(), nl); + } } } #endif From 0f3f731254dd92f2b0e20587639ed4883999eeb3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 11 Jun 2024 08:57:02 +0200 Subject: [PATCH 21/37] Handle -work for vhdl, and clean messages --- frontends/verific/verific.cc | 37 +++++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 7 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index e7bc24219..0a8d432a3 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -42,6 +42,8 @@ USING_YOSYS_NAMESPACE #pragma clang diagnostic ignored "-Woverloaded-virtual" #endif +#include "Array.h" +#include "RuntimeFlags.h" #ifdef VERIFIC_HIER_TREE_SUPPORT #include "hier_tree.h" #endif @@ -84,6 +86,10 @@ USING_YOSYS_NAMESPACE #endif #endif +#if !defined(VERIFIC_VHDL_SUPPORT) && !defined(VERIFIC_SYSTEMVERILOG_SUPPORT) +#error "At least one of HDL languages must be enabled." +#endif + #ifdef __clang__ #pragma clang diagnostic pop #endif @@ -2814,7 +2820,7 @@ std::string verific_import(Design *design, const std::mapInsertLast(Netlist::PresentDesign()); -#else +#elif defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && defined(VERIFIC_VHDL_SUPPORT) // Both SystemVerilog and VHDL support if (veri_modules.Size()>0) netlists = veri_file::ElaborateMultipleTop(&veri_modules, &verific_params); @@ -2824,6 +2830,7 @@ std::string verific_import(Design *design, const std::mapInsertLast(Netlist::PresentDesign()); } +#else #endif #endif } @@ -3452,6 +3459,7 @@ struct VerificPass : public Pass { } veri_file::RemoveAllLOptions(); +#endif for (int i = argidx; i < GetSize(args); i++) { if (args[i] == "-work" && i+1 < GetSize(args)) { @@ -3459,24 +3467,30 @@ struct VerificPass : public Pass { is_work_set = true; continue; } +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (args[i] == "-L" && i+1 < GetSize(args)) { ++i; continue; } +#endif break; } +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT veri_file::AddLOption(work.c_str()); +#endif for (int i = argidx; i < GetSize(args); i++) { if (args[i] == "-work" && i+1 < GetSize(args)) { ++i; continue; } +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (args[i] == "-L" && i+1 < GetSize(args)) { if (args[++i] == work) veri_file::RemoveAllLOptions(); continue; } +#endif break; } for (; argidx < GetSize(args); argidx++) @@ -3486,13 +3500,16 @@ struct VerificPass : public Pass { is_work_set = true; continue; } +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (args[argidx] == "-L" && argidx+1 < GetSize(args)) { veri_file::AddLOption(args[++argidx].c_str()); continue; } +#endif break; } +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F")) { unsigned verilog_mode = veri_file::UNDEFINED; @@ -3966,8 +3983,6 @@ struct VerificPass : public Pass { if (!ppfile.empty()) veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str()); #endif - log("Running hier_tree::ElaborateAll().\n"); - Array vhdl_libs; #ifdef VERIFIC_VHDL_SUPPORT VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); @@ -3980,6 +3995,7 @@ struct VerificPass : public Pass { #endif #ifdef VERIFIC_HIER_TREE_SUPPORT + log("Running hier_tree::ElaborateAll().\n"); Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, ¶meters); Netlist *nl; int i; @@ -3991,9 +4007,11 @@ struct VerificPass : public Pass { if (parameters.Size()) log_warning("Please note that parameters are not propagated during import.\n"); #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT + log("Running veri_file::ElaborateAll().\n"); veri_file::ElaborateAll(work.c_str()); #endif #ifdef VERIFIC_VHDL_SUPPORT + log("Running vhdl_file::ElaborateAll().\n"); vhdl_file::ElaborateAll(work.c_str()); #endif MapIter mi ; @@ -4107,32 +4125,37 @@ struct VerificPass : public Pass { } } #endif - log("Running hier_tree::Elaborate().\n"); #ifdef VERIFIC_HIER_TREE_SUPPORT + log("Running hier_tree::Elaborate().\n"); netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, ¶meters); #else #if defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && !defined(VERIFIC_VHDL_SUPPORT) + log("Running veri_file::ElaborateMultipleTop().\n"); // SystemVerilog support only netlists = veri_file::ElaborateMultipleTop(&veri_modules, ¶meters); #elif defined(VERIFIC_VHDL_SUPPORT) && !defined(VERIFIC_SYSTEMVERILOG_SUPPORT) + log("Running vhdl_file::Elaborate().\n"); // VHDL support only netlists = new Array(top_mod_names.size()); for (auto &name : top_mod_names) { vhdl_file::Elaborate(name.c_str(), work.c_str(), 0, ¶meters); netlists->InsertLast(Netlist::PresentDesign()); } -#else +#elif defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && defined(VERIFIC_VHDL_SUPPORT) // Both SystemVerilog and VHDL support - if (veri_modules.Size()>0) + if (veri_modules.Size()>0) { + log("Running veri_file::ElaborateMultipleTop().\n"); netlists = veri_file::ElaborateMultipleTop(&veri_modules, ¶meters); - else + } else netlists = new Array(1); if (vhdl_units.Size()>0) { + log("Running vhdl_file::Elaborate().\n"); for (auto &name : top_mod_names) { vhdl_file::Elaborate(name.c_str(), work.c_str(), 0, ¶meters); netlists->InsertLast(Netlist::PresentDesign()); } } +#else #endif #endif } From 19da7f7d59fd3c01f677631652c695815208da86 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 11 Jun 2024 15:32:16 +0200 Subject: [PATCH 22/37] Update makefile to make options uniform --- Makefile | 20 ++++++++++++-------- frontends/verific/Makefile.inc | 2 +- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/Makefile b/Makefile index 0712e987b..b86eb4bfa 100644 --- a/Makefile +++ b/Makefile @@ -17,12 +17,12 @@ ENABLE_READLINE := 1 ENABLE_EDITLINE := 0 ENABLE_GHDL := 0 ENABLE_VERIFIC := 0 +ENABLE_VERIFIC_SYSTEMVERILOG := 1 +ENABLE_VERIFIC_VHDL := 1 +ENABLE_VERIFIC_HIER_TREE := 1 +ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1 ENABLE_VERIFIC_EDIF := 0 ENABLE_VERIFIC_LIBERTY := 0 -DISABLE_VERIFIC_EXTENSIONS := 0 -DISABLE_VERIFIC_SYSTEMVERILOG := 0 -DISABLE_VERIFIC_VHDL := 0 -DISABLE_VERIFIC_HIER_TREE := 0 ENABLE_COVER := 1 ENABLE_LIBYOSYS := 0 ENABLE_ZLIB := 1 @@ -474,7 +474,7 @@ LIBS_VERIFIC = ifeq ($(ENABLE_VERIFIC),1) VERIFIC_DIR ?= /usr/local/src/verific_lib VERIFIC_COMPONENTS ?= database util containers -ifneq ($(DISABLE_VERIFIC_HIER_TREE),1) +ifeq ($(ENABLE_VERIFIC_HIER_TREE),1) VERIFIC_COMPONENTS += hier_tree CXXFLAGS += -DVERIFIC_HIER_TREE_SUPPORT else @@ -482,7 +482,7 @@ ifneq ($(wildcard $(VERIFIC_DIR)/hier_tree),) VERIFIC_COMPONENTS += hier_tree endif endif -ifneq ($(DISABLE_VERIFIC_SYSTEMVERILOG),1) +ifeq ($(ENABLE_VERIFIC_SYSTEMVERILOG),1) VERIFIC_COMPONENTS += verilog CXXFLAGS += -DVERIFIC_SYSTEMVERILOG_SUPPORT else @@ -490,7 +490,7 @@ ifneq ($(wildcard $(VERIFIC_DIR)/verilog),) VERIFIC_COMPONENTS += verilog endif endif -ifneq ($(DISABLE_VERIFIC_VHDL),1) +ifeq ($(ENABLE_VERIFIC_VHDL),1) VERIFIC_COMPONENTS += vhdl CXXFLAGS += -DVERIFIC_VHDL_SUPPORT else @@ -506,9 +506,13 @@ ifeq ($(ENABLE_VERIFIC_LIBERTY),1) VERIFIC_COMPONENTS += synlib CXXFLAGS += -DVERIFIC_LIBERTY_SUPPORT endif -ifneq ($(DISABLE_VERIFIC_EXTENSIONS),1) +ifeq ($(ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS),1) VERIFIC_COMPONENTS += extensions CXXFLAGS += -DYOSYSHQ_VERIFIC_EXTENSIONS +else +ifneq ($(wildcard $(VERIFIC_DIR)/extensions),) +VERIFIC_COMPONENTS += extensions +endif endif CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC ifeq ($(OS), Darwin) diff --git a/frontends/verific/Makefile.inc b/frontends/verific/Makefile.inc index df3ac8d2d..0766240a4 100644 --- a/frontends/verific/Makefile.inc +++ b/frontends/verific/Makefile.inc @@ -10,7 +10,7 @@ EXTRA_TARGETS += share/verific share/verific: $(P) rm -rf share/verific.new $(Q) mkdir -p share/verific.new -ifneq ($(DISABLE_VERIFIC_VHDL),1) +ifeq ($(ENABLE_VERIFIC_VHDL),1) $(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1987/. share/verific.new/vhdl_vdbs_1987 $(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1993/. share/verific.new/vhdl_vdbs_1993 $(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008/. share/verific.new/vhdl_vdbs_2008 From dfde792288fd9e42bd101c56a81699abc2c450af Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 17 Jun 2024 14:49:58 +0200 Subject: [PATCH 23/37] Refactored import code --- frontends/verific/verific.cc | 533 +++++++++++++---------------------- 1 file changed, 200 insertions(+), 333 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 0a8d432a3..56e94489c 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2696,183 +2696,217 @@ struct VerificExtNets } }; -std::string verific_import(Design *design, const std::map ¶meters, std::string top) +void import_all(const char* work, std::map *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED) { - verific_sva_fsm_limit = 16; +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + VerificExtensions::ElaborateAndRewrite(work, parameters); + verific_error_msg.clear(); +#endif +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT + if (!ppfile.empty()) + veri_file::PrettyPrint(ppfile.c_str(), nullptr, work); +#endif - std::map nl_todo, nl_done; - Array *netlists = NULL; Array vhdl_libs; #ifdef VERIFIC_VHDL_SUPPORT - VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1); + VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work, 1); if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib); #endif Array veri_libs; #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1); + VeriLibrary *veri_lib = veri_file::GetLibrary(work, 1); if (veri_lib) veri_libs.InsertLast(veri_lib); #endif - Map verific_params(STRING_HASH); - for (const auto &i : parameters) - verific_params.Insert(i.first.c_str(), i.second.c_str()); - - if (top.empty()) { - -#ifdef YOSYSHQ_VERIFIC_EXTENSIONS - VerificExtensions::ElaborateAndRewrite("work", &verific_params); - verific_error_msg.clear(); -#endif #ifdef VERIFIC_HIER_TREE_SUPPORT - netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params); + if (show_message) + log("Running hier_tree::ElaborateAll().\n"); + Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, parameters); + Netlist *nl; + int i; + + FOREACH_ARRAY_ITEM(netlists, i, nl) + nl_todo->emplace(nl->CellBaseName(), nl); + delete netlists; #else - if (parameters.size()) - log_warning("Please note that parameters are not propagated during import.\n"); + if (parameters->Size()) + log_warning("Please note that parameters are not propagated during import.\n"); #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - veri_file::ElaborateAll("work"); + if (show_message) + log("Running veri_file::ElaborateAll().\n"); + veri_file::ElaborateAll(work); #endif #ifdef VERIFIC_VHDL_SUPPORT - vhdl_file::ElaborateAll("work"); + if (show_message) + log("Running vhdl_file::ElaborateAll().\n"); + vhdl_file::ElaborateAll(work); #endif - netlists = new Array(1); - MapIter mi ; - Verific::Cell *c ; - MapIter it ; - Library *l ; - FOREACH_LIBRARY_OF_LIBSET(Libset::Global(),it,l) { - if (l == Library::Primitives() || l == Library::Operators()) continue; - FOREACH_CELL_OF_LIBRARY(l,mi,c) { - MapIter ni ; - Netlist *nl; - FOREACH_NETLIST_OF_CELL(c, ni, nl) { - if (nl) - netlists->InsertLast(nl); - } + MapIter mi ; + Verific::Cell *c ; + MapIter it ; + Library *l ; + FOREACH_LIBRARY_OF_LIBSET(Libset::Global(),it,l) { + if (l == Library::Primitives() || l == Library::Operators()) continue; + FOREACH_CELL_OF_LIBRARY(l,mi,c) { + MapIter ni ; + Netlist *nl; + FOREACH_NETLIST_OF_CELL(c, ni, nl) { + if (nl) + nl_todo->emplace(nl->CellBaseName(), nl); } } -#endif } - else { +#endif +} + +std::set import_tops(const char* work, std::map *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED, std::vector &tops) +{ + std::set top_mod_names; + Array *netlists = nullptr; + +#ifdef VERIFIC_VHDL_SUPPORT + VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work, 1); +#endif +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT + VeriLibrary* veri_lib = veri_file::GetLibrary(work, 1); +#endif #ifdef YOSYSHQ_VERIFIC_EXTENSIONS - for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--) + for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--) #endif + { + Array vhdl_units; + Array veri_modules; + for (std::string n : tops) { - Array veri_modules; + const char *name = n.c_str(); + top_mod_names.insert(name); + #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - if (veri_lib) { - VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1); - if (veri_module) { + VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr; + if (veri_module) { + if (veri_module->IsConfiguration()) { + if (show_message) + log("Adding Verilog configuration '%s' to elaboration queue.\n", name); veri_modules.InsertLast(veri_module); - if (veri_module->IsConfiguration()) { - VeriConfiguration *cfg = (VeriConfiguration*)veri_module; - VeriName *module_name = (VeriName*)cfg->GetTopModuleNames()->GetLast(); + top_mod_names.erase(name); + VeriConfiguration *cfg = (VeriConfiguration*)veri_module; + VeriName *module_name; + int i; + FOREACH_ARRAY_ITEM(cfg->GetTopModuleNames(), i, module_name) { VeriLibrary *lib = veri_module->GetLibrary() ; if (module_name && module_name->IsHierName()) { VeriName *prefix = module_name->GetPrefix() ; const char *lib_name = (prefix) ? prefix->GetName() : 0 ; - if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ; + if (work != lib_name) lib = veri_file::GetLibrary(lib_name, 1) ; } if (lib && module_name) - top = lib->GetModule(module_name->GetName(), 1)->GetName(); - } - } - -#ifdef YOSYSHQ_VERIFIC_EXTENSIONS - if (!static_elaborate) -#endif - { - // Also elaborate all root modules since they may contain bind statements - MapIter mi; - FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) { - if (!veri_module->IsRootModule()) continue; - veri_modules.InsertLast(veri_module); + top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName()); } + } else { + if (show_message) + log("Adding Verilog module '%s' to elaboration queue.\n", name); + veri_modules.InsertLast(veri_module); } + continue; } #endif - - Array vhdl_units; #ifdef VERIFIC_VHDL_SUPPORT - if (vhdl_lib) { - VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(top.c_str()); - if (vhdl_unit) - vhdl_units.InsertLast(vhdl_unit); - } -#endif - -#ifdef YOSYSHQ_VERIFIC_EXTENSIONS - if (static_elaborate) { - VerificExtensions::ElaborateAndRewrite("work", &veri_modules, &vhdl_units, &verific_params); - verific_error_msg.clear(); + VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr; + if (vhdl_unit) { + if (show_message) + log("Adding VHDL unit '%s' to elaboration queue.\n", name); + vhdl_units.InsertLast(vhdl_unit); continue; } #endif + log_error("Can't find module/unit '%s'.\n", name); + } +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + if (static_elaborate) { + VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, parameters); + verific_error_msg.clear(); +#endif +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT + if (!ppfile.empty()) + veri_file::PrettyPrint(ppfile.c_str(), nullptr, work); +#endif +#ifdef YOSYSHQ_VERIFIC_EXTENSIONS + continue; + } +#endif +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT + const char *lib_name = nullptr; + SetIter si; + FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) { + VeriLibrary* veri_lib = veri_file::GetLibrary(lib_name, 0); + if (veri_lib) { + // Also elaborate all root modules since they may contain bind statements + MapIter mi; + VeriModule *veri_module; + FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) { + if (!veri_module->IsRootModule()) continue; + veri_modules.InsertLast(veri_module); + } + } + } +#endif #ifdef VERIFIC_HIER_TREE_SUPPORT - netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params); + if (show_message) + log("Running hier_tree::Elaborate().\n"); + netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, parameters); #else #if defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && !defined(VERIFIC_VHDL_SUPPORT) - // SystemVerilog support only - netlists = veri_file::ElaborateMultipleTop(&veri_modules, &verific_params); + if (show_message) + log("Running veri_file::ElaborateMultipleTop().\n"); + // SystemVerilog support only + netlists = veri_file::ElaborateMultipleTop(&veri_modules, parameters); #elif defined(VERIFIC_VHDL_SUPPORT) && !defined(VERIFIC_SYSTEMVERILOG_SUPPORT) - // VHDL support only - netlists = new Array(1); - vhdl_file::Elaborate(top.c_str(), "work", 0, &verific_params); + if (show_message) + log("Running vhdl_file::Elaborate().\n"); + // VHDL support only + netlists = new Array(top_mod_names.size()); + for (auto &name : top_mod_names) { + vhdl_file::Elaborate(name.c_str(), work, 0, parameters); netlists->InsertLast(Netlist::PresentDesign()); + } #elif defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && defined(VERIFIC_VHDL_SUPPORT) - // Both SystemVerilog and VHDL support - if (veri_modules.Size()>0) - netlists = veri_file::ElaborateMultipleTop(&veri_modules, &verific_params); - else - netlists = new Array(1); - if (vhdl_units.Size()>0) { - vhdl_file::Elaborate(top.c_str(), "work", 0, &verific_params); + // Both SystemVerilog and VHDL support + if (veri_modules.Size()>0) { + if (show_message) + log("Running veri_file::ElaborateMultipleTop().\n"); + netlists = veri_file::ElaborateMultipleTop(&veri_modules, parameters); + } else + netlists = new Array(1); + if (vhdl_units.Size()>0) { + if (show_message) + log("Running vhdl_file::Elaborate().\n"); + for (auto &name : top_mod_names) { + vhdl_file::Elaborate(name.c_str(), work, 0, parameters); netlists->InsertLast(Netlist::PresentDesign()); } + } #else #endif #endif - } } - Netlist *nl; int i; - std::string cell_name = top; FOREACH_ARRAY_ITEM(netlists, i, nl) { if (!nl) continue; - if (!top.empty() && nl->CellBaseName() != top) + if (!top_mod_names.count(nl->CellBaseName())) continue; nl->AddAtt(new Att(" \\top", NULL)); - nl_todo.emplace(nl->CellBaseName(), nl); - cell_name = nl->CellBaseName(); + nl_todo->emplace(nl->CellBaseName(), nl); } - if (top.empty()) cell_name = top; - delete netlists; + return top_mod_names; +} - if (!verific_error_msg.empty()) - log_error("%s\n", verific_error_msg.c_str()); - - for (auto nl : nl_todo) - nl.second->ChangePortBusStructures(1 /* hierarchical */); - - VerificExtNets worker; - for (auto nl : nl_todo) - worker.run(nl.second); - - while (!nl_todo.empty()) { - auto it = nl_todo.begin(); - Netlist *nl = it->second; - if (nl_done.count(it->first) == 0) { - VerificImporter importer(false, false, false, false, false, false, false); - nl_done[it->first] = it->second; - importer.import_netlist(design, nl, nl_todo, nl->CellBaseName() == cell_name); - } - nl_todo.erase(it); - } - +void verific_cleanup() +{ #ifdef YOSYSHQ_VERIFIC_EXTENSIONS VerificExtensions::Reset(); #endif @@ -2901,7 +2935,53 @@ std::string verific_import(Design *design, const std::map ¶meters, std::string top) +{ + verific_sva_fsm_limit = 16; + + std::map nl_todo, nl_done; + + Map verific_params(STRING_HASH); + for (const auto &i : parameters) + verific_params.Insert(i.first.c_str(), i.second.c_str()); + + std::set top_mod_names; + if (top.empty()) { + import_all("work", &nl_todo, &verific_params, false, ""); + } else { + std::vector tops; + tops.push_back(top); +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT + veri_file::RemoveAllLOptions(); + veri_file::AddLOption("work"); +#endif + top_mod_names = import_tops("work", &nl_todo, &verific_params, false, "", tops) ; + } + + if (!verific_error_msg.empty()) + log_error("%s\n", verific_error_msg.c_str()); + + for (auto nl : nl_todo) + nl.second->ChangePortBusStructures(1 /* hierarchical */); + + VerificExtNets worker; + for (auto nl : nl_todo) + worker.run(nl.second); + + while (!nl_todo.empty()) { + auto it = nl_todo.begin(); + Netlist *nl = it->second; + if (nl_done.count(it->first) == 0) { + VerificImporter importer(false, false, false, false, false, false, false); + nl_done[it->first] = it->second; + importer.import_netlist(design, nl, nl_todo, top_mod_names.count(nl->CellBaseName())); + } + nl_todo.erase(it); + } + + verific_cleanup(); if (!verific_error_msg.empty()) log_error("%s\n", verific_error_msg.c_str()); return top; @@ -3974,203 +4054,17 @@ struct VerificPass : public Pass { if (mode_all) { - -#ifdef YOSYSHQ_VERIFIC_EXTENSIONS - VerificExtensions::ElaborateAndRewrite(work, ¶meters); - verific_error_msg.clear(); -#endif -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - if (!ppfile.empty()) - veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str()); -#endif - Array vhdl_libs; -#ifdef VERIFIC_VHDL_SUPPORT - VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); - if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib); -#endif - Array veri_libs; -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1); - if (veri_lib) veri_libs.InsertLast(veri_lib); -#endif - -#ifdef VERIFIC_HIER_TREE_SUPPORT - log("Running hier_tree::ElaborateAll().\n"); - Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, ¶meters); - Netlist *nl; - int i; - - FOREACH_ARRAY_ITEM(netlists, i, nl) - nl_todo.emplace(nl->CellBaseName(), nl); - delete netlists; -#else - if (parameters.Size()) - log_warning("Please note that parameters are not propagated during import.\n"); -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - log("Running veri_file::ElaborateAll().\n"); - veri_file::ElaborateAll(work.c_str()); -#endif -#ifdef VERIFIC_VHDL_SUPPORT - log("Running vhdl_file::ElaborateAll().\n"); - vhdl_file::ElaborateAll(work.c_str()); -#endif - MapIter mi ; - Verific::Cell *c ; - MapIter it ; - Library *l ; - FOREACH_LIBRARY_OF_LIBSET(Libset::Global(),it,l) { - if (l == Library::Primitives() || l == Library::Operators()) continue; - FOREACH_CELL_OF_LIBRARY(l,mi,c) { - MapIter ni ; - Netlist *nl; - FOREACH_NETLIST_OF_CELL(c, ni, nl) { - if (nl) - nl_todo.emplace(nl->CellBaseName(), nl); - } - } - } -#endif + import_all(work.c_str(), &nl_todo, ¶meters, true, ppfile); } else { if (argidx == GetSize(args)) cmd_error(args, argidx, "No top module specified.\n"); - Array *netlists = nullptr; - -#ifdef YOSYSHQ_VERIFIC_EXTENSIONS - for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--) -#endif - { - - Array vhdl_units; -#ifdef VERIFIC_VHDL_SUPPORT - VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); -#endif - Array veri_modules; -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1); -#endif - for (int i = argidx; i < GetSize(args); i++) - { - const char *name = args[i].c_str(); - top_mod_names.insert(name); - -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr; - if (veri_module) { - if (veri_module->IsConfiguration()) { - log("Adding Verilog configuration '%s' to elaboration queue.\n", name); - veri_modules.InsertLast(veri_module); - - top_mod_names.erase(name); - - VeriConfiguration *cfg = (VeriConfiguration*)veri_module; - VeriName *module_name; - int i; - FOREACH_ARRAY_ITEM(cfg->GetTopModuleNames(), i, module_name) { - VeriLibrary *lib = veri_module->GetLibrary() ; - if (module_name && module_name->IsHierName()) { - VeriName *prefix = module_name->GetPrefix() ; - const char *lib_name = (prefix) ? prefix->GetName() : 0 ; - if (work != lib_name) lib = veri_file::GetLibrary(lib_name, 1) ; - } - if (lib && module_name) - top_mod_names.insert(lib->GetModule(module_name->GetName(), 1)->GetName()); - } - } else { - log("Adding Verilog module '%s' to elaboration queue.\n", name); - veri_modules.InsertLast(veri_module); - } - continue; - } -#endif -#ifdef VERIFIC_VHDL_SUPPORT - VhdlDesignUnit *vhdl_unit = vhdl_lib ? vhdl_lib->GetPrimUnit(name) : nullptr; - if (vhdl_unit) { - log("Adding VHDL unit '%s' to elaboration queue.\n", name); - vhdl_units.InsertLast(vhdl_unit); - continue; - } -#endif - log_error("Can't find module/unit '%s'.\n", name); - } - -#ifdef YOSYSHQ_VERIFIC_EXTENSIONS - if (static_elaborate) { - VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, ¶meters); - verific_error_msg.clear(); -#endif -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - if (!ppfile.empty()) - veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str()); -#endif -#ifdef YOSYSHQ_VERIFIC_EXTENSIONS - continue; - } -#endif -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - const char *lib_name = nullptr; - SetIter si; - FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) { - VeriLibrary* veri_lib = veri_file::GetLibrary(lib_name, 0); - if (veri_lib) { - // Also elaborate all root modules since they may contain bind statements - MapIter mi; - VeriModule *veri_module; - FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) { - if (!veri_module->IsRootModule()) continue; - veri_modules.InsertLast(veri_module); - } - } - } -#endif -#ifdef VERIFIC_HIER_TREE_SUPPORT - log("Running hier_tree::Elaborate().\n"); - netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, ¶meters); -#else -#if defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && !defined(VERIFIC_VHDL_SUPPORT) - log("Running veri_file::ElaborateMultipleTop().\n"); - // SystemVerilog support only - netlists = veri_file::ElaborateMultipleTop(&veri_modules, ¶meters); -#elif defined(VERIFIC_VHDL_SUPPORT) && !defined(VERIFIC_SYSTEMVERILOG_SUPPORT) - log("Running vhdl_file::Elaborate().\n"); - // VHDL support only - netlists = new Array(top_mod_names.size()); - for (auto &name : top_mod_names) { - vhdl_file::Elaborate(name.c_str(), work.c_str(), 0, ¶meters); - netlists->InsertLast(Netlist::PresentDesign()); - } -#elif defined(VERIFIC_SYSTEMVERILOG_SUPPORT) && defined(VERIFIC_VHDL_SUPPORT) - // Both SystemVerilog and VHDL support - if (veri_modules.Size()>0) { - log("Running veri_file::ElaborateMultipleTop().\n"); - netlists = veri_file::ElaborateMultipleTop(&veri_modules, ¶meters); - } else - netlists = new Array(1); - if (vhdl_units.Size()>0) { - log("Running vhdl_file::Elaborate().\n"); - for (auto &name : top_mod_names) { - vhdl_file::Elaborate(name.c_str(), work.c_str(), 0, ¶meters); - netlists->InsertLast(Netlist::PresentDesign()); - } - } -#else -#endif -#endif - } - - Netlist *nl; - int i; - - FOREACH_ARRAY_ITEM(netlists, i, nl) { - if (!nl) continue; - if (!top_mod_names.count(nl->CellBaseName())) - continue; - nl->AddAtt(new Att(" \\top", NULL)); - nl_todo.emplace(nl->CellBaseName(), nl); - } - delete netlists; + std::vector tops; + for (int i = argidx; i < GetSize(args); i++) + tops.push_back(args[i].c_str()); + top_mod_names = import_tops(work.c_str(), &nl_todo, ¶meters, true, ppfile, tops) ; } if (mode_cells) { log("Importing all cells.\n"); @@ -4232,34 +4126,7 @@ struct VerificPass : public Pass { nl_todo.erase(it); } -#ifdef YOSYSHQ_VERIFIC_EXTENSIONS - VerificExtensions::Reset(); -#endif -#ifdef VERIFIC_HIER_TREE_SUPPORT - hier_tree::DeleteHierarchicalTree(); -#endif -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - veri_file::Reset(); -#endif -#ifdef VERIFIC_VHDL_SUPPORT - vhdl_file::Reset(); -#endif -#ifdef VERIFIC_EDIF_SUPPORT - edif_file::Reset(); -#endif -#ifdef VERIFIC_LIBERTY_SUPPORT - synlib_file::Reset(); -#endif - Libset::Reset(); - Message::Reset(); - RuntimeFlags::DeleteAllFlags(); - LineFile::DeleteAllLineFiles(); -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - verific_incdirs.clear(); - verific_libdirs.clear(); - verific_libexts.clear(); -#endif - verific_import_pending = false; + verific_cleanup(); goto check_error; } From 141a2e36389795b3e6e9cae82c8639843446c4db Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 17 Jun 2024 16:55:36 +0200 Subject: [PATCH 24/37] Make C++17 compiler required --- .github/workflows/test-compile.yml | 4 ++-- Makefile | 4 ++-- kernel/yosys_common.h | 6 +----- 3 files changed, 5 insertions(+), 9 deletions(-) diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml index 375ea7fc5..a892c91ce 100644 --- a/.github/workflows/test-compile.yml +++ b/.github/workflows/test-compile.yml @@ -64,11 +64,11 @@ jobs: $CXX --version # minimum standard - - name: Build C++11 + - name: Build C++17 shell: bash run: | make config-$CC_SHORT - make -j$procs CXXSTD=c++11 compile-only + make -j$procs CXXSTD=c++17 compile-only # maximum standard, only on newest compilers - name: Build C++20 diff --git a/Makefile b/Makefile index 7760cec43..73ea0bcc1 100644 --- a/Makefile +++ b/Makefile @@ -90,7 +90,7 @@ all: top-all YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST))) VPATH := $(YOSYS_SRC) -CXXSTD ?= c++11 +CXXSTD ?= c++17 CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include LIBS := $(LIBS) -lstdc++ -lm PLUGIN_LINKFLAGS := @@ -1015,7 +1015,7 @@ qtcreator: vcxsrc: $(GENFILES) $(EXTRA_TARGETS) rm -rf yosys-win32-vcxsrc-$(YOSYS_VER){,.zip} set -e; for f in `ls $(filter %.cc %.cpp,$(GENFILES)) $(addsuffix .cc,$(basename $(OBJS))) $(addsuffix .cpp,$(basename $(OBJS))) 2> /dev/null`; do \ - echo "Analyse: $$f" >&2; cpp -std=c++11 -MM -I. -D_YOSYS_ $$f; done | sed 's,.*:,,; s,//*,/,g; s,/[^/]*/\.\./,/,g; y, \\,\n\n,;' | grep '^[^/]' | sort -u | grep -v kernel/version_ > srcfiles.txt + echo "Analyse: $$f" >&2; cpp -std=c++17 -MM -I. -D_YOSYS_ $$f; done | sed 's,.*:,,; s,//*,/,g; s,/[^/]*/\.\./,/,g; y, \\,\n\n,;' | grep '^[^/]' | sort -u | grep -v kernel/version_ > srcfiles.txt bash misc/create_vcxsrc.sh yosys-win32-vcxsrc $(YOSYS_VER) $(GIT_REV) echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys (Version Information Unavailable)\"; }" > kernel/version.cc zip yosys-win32-vcxsrc-$(YOSYS_VER)/genfiles.zip $(GENFILES) kernel/version.cc diff --git a/kernel/yosys_common.h b/kernel/yosys_common.h index 9f1bc2f58..56d2356b1 100644 --- a/kernel/yosys_common.h +++ b/kernel/yosys_common.h @@ -142,12 +142,8 @@ extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *p #if __cplusplus >= 201703L # define YS_FALLTHROUGH [[fallthrough]]; -#elif defined(__clang__) -# define YS_FALLTHROUGH [[clang::fallthrough]]; -#elif defined(__GNUC__) -# define YS_FALLTHROUGH [[gnu::fallthrough]]; #else -# define YS_FALLTHROUGH +# error "C++17 or later compatible compiler is required" #endif From f9b7b8fff0cf72c293a26818734dd41853a1e511 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 17 Jun 2024 17:08:13 +0200 Subject: [PATCH 25/37] Update documentation for C++17 switch --- README.md | 2 +- docs/source/getting_started/installation.rst | 2 +- docs/source/yosys_internals/index.rst | 2 +- guidelines/CodingStyle | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 4647efbe9..bb1c4d443 100644 --- a/README.md +++ b/README.md @@ -71,7 +71,7 @@ Many Linux distributions also provide Yosys binaries, some more up to date than Building from Source ==================== -You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is +You need a C++ compiler with C++17 support (up-to-date CLANG or GCC is recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make. TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile). Xdot (graphviz) is used by the ``show`` command in yosys to display schematics. diff --git a/docs/source/getting_started/installation.rst b/docs/source/getting_started/installation.rst index 4dd5244b9..1a8988608 100644 --- a/docs/source/getting_started/installation.rst +++ b/docs/source/getting_started/installation.rst @@ -84,7 +84,7 @@ not regularly tested: Build prerequisites ^^^^^^^^^^^^^^^^^^^ -A C++ compiler with C++11 support is required as well as some standard tools +A C++ compiler with C++17 support is required as well as some standard tools such as GNU Flex, GNU Bison, Make and Python. Some additional tools: readline, libffi, Tcl and zlib; are optional but enabled by default (see :makevar:`ENABLE_*` settings in Makefile). Graphviz and Xdot are used by the diff --git a/docs/source/yosys_internals/index.rst b/docs/source/yosys_internals/index.rst index b04f13699..efd865623 100644 --- a/docs/source/yosys_internals/index.rst +++ b/docs/source/yosys_internals/index.rst @@ -25,7 +25,7 @@ wide range of real-world designs, including the `OpenRISC 1200 CPU`_, the .. _k68 CPU: http://opencores.org/projects/k68 -Yosys is written in C++, targeting C++11 at minimum. This chapter describes some +Yosys is written in C++, targeting C++17 at minimum. This chapter describes some of the fundamental Yosys data structures. For the sake of simplicity the C++ type names used in the Yosys implementation are used in this chapter, even though the chapter only explains the conceptual idea behind it and can be used diff --git a/guidelines/CodingStyle b/guidelines/CodingStyle index 8a3df2d62..491507cdd 100644 --- a/guidelines/CodingStyle +++ b/guidelines/CodingStyle @@ -25,7 +25,7 @@ Formatting of code C++ Language ------------- -Yosys is written in C++11. +Yosys is written in C++17. In general Yosys uses "int" instead of "size_t". To avoid compiler warnings for implicit type casts, always use "GetSize(foobar)" instead From 2bbf3112d998635930584dc7113755a12f1be27e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 17 Jun 2024 17:29:20 +0200 Subject: [PATCH 26/37] Update VS build to C++17 build --- misc/create_vcxsrc.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/misc/create_vcxsrc.sh b/misc/create_vcxsrc.sh index eee215015..5f8b35e80 100644 --- a/misc/create_vcxsrc.sh +++ b/misc/create_vcxsrc.sh @@ -30,6 +30,7 @@ popd tail -n +$((n+1)) "$vcxsrc"/YosysVS/YosysVS.vcxproj } > "$vcxsrc"/YosysVS/YosysVS.vcxproj.new +sed -i 's,,\n stdcpp17\n /Zc:__cplusplus %(AdditionalOptions),g' "$vcxsrc"/YosysVS/YosysVS.vcxproj.new mv "$vcxsrc"/YosysVS/YosysVS.vcxproj.new "$vcxsrc"/YosysVS/YosysVS.vcxproj mkdir -p "$vcxsrc"/yosys From ede3750a6c8c178cabe8595155cf48e82725f222 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Wed, 19 Jun 2024 00:17:13 +0000 Subject: [PATCH 27/37] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index b86eb4bfa..583c0e05e 100644 --- a/Makefile +++ b/Makefile @@ -143,7 +143,7 @@ LIBS += -lrt endif endif -YOSYS_VER := 0.42+15 +YOSYS_VER := 0.42+28 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 22d8df1e7e08994bef3d67bac144001397b95c2f Mon Sep 17 00:00:00 2001 From: gatecat Date: Mon, 10 Jun 2024 16:29:11 +0200 Subject: [PATCH 28/37] liberty: Support for IO liberty files for verification Signed-off-by: gatecat --- frontends/liberty/liberty.cc | 38 ++++++++++++++++++++++++++---------- 1 file changed, 28 insertions(+), 10 deletions(-) diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index cadbcaee6..86bb4c7dc 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -214,6 +214,18 @@ static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr) return stack.back().sig; } +static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func, const char *three_state_expr) +{ + RTLIL::SigSpec three_state = parse_func_expr(module, three_state_expr); + + RTLIL::Cell *cell = module->addCell(NEW_ID, ID($tribuf)); + cell->setParam(ID::WIDTH, GetSize(func)); + cell->setPort(ID::A, func); + cell->setPort(ID::EN, create_inv_cell(module, three_state)); + cell->setPort(ID::Y, module->addWire(NEW_ID)); + return cell->getPort(ID::Y); +} + static void create_ff(RTLIL::Module *module, LibertyAst *node) { RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0)))); @@ -695,18 +707,24 @@ struct LibertyFrontend : public Frontend { LibertyAst *func = node->find("function"); if (func == NULL) { - if (!flag_ignore_miss_func) - { - log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name)); - } else { - log("Ignoring cell %s with missing function on output %s.\n", log_id(module->name), log_id(wire->name)); - delete module; - goto skip_cell; + if (dir->value != "inout") { // allow inout with missing function, can be used for power pins + if (!flag_ignore_miss_func) + { + log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name)); + } else { + log("Ignoring cell %s with missing function on output %s.\n", log_id(module->name), log_id(wire->name)); + delete module; + goto skip_cell; + } } + } else { + RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str()); + LibertyAst *three_state = node->find("three_state"); + if (three_state) { + out_sig = create_tristate(module, out_sig, three_state->value.c_str()); + } + module->connect(RTLIL::SigSig(wire, out_sig)); } - - RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str()); - module->connect(RTLIL::SigSig(wire, out_sig)); } } From 6c8ae44ae7ebe5cbad7cfaf2d0934701e29c9527 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 20 Jun 2024 00:17:08 +0000 Subject: [PATCH 29/37] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 583c0e05e..d2c56e979 100644 --- a/Makefile +++ b/Makefile @@ -143,7 +143,7 @@ LIBS += -lrt endif endif -YOSYS_VER := 0.42+28 +YOSYS_VER := 0.42+30 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 89d939334eab09b8dd7baea71b4b23b87345dc7d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Fri, 21 Jun 2024 15:14:08 +0200 Subject: [PATCH 30/37] rtlil: Fix `addShiftx` for signed shifts Only the `B` input (the shift amount) can be marked as signed on a `$shiftx` cell. Adapt the helper accordingly and prevent it from creating invalid RTLIL when called with `is_signed` set. Previously it would mark both `A` and `B` as signed. --- kernel/rtlil.cc | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a6aebaa42..d3946a620 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2517,7 +2517,6 @@ DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or)) DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor)) DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor)) DEF_METHOD(Shift, sig_a.size(), ID($shift)) -DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx)) DEF_METHOD(Lt, 1, ID($lt)) DEF_METHOD(Le, 1, ID($le)) DEF_METHOD(Eq, 1, ID($eq)) @@ -2562,6 +2561,28 @@ DEF_METHOD(Sshl, sig_a.size(), ID($sshl)) DEF_METHOD(Sshr, sig_a.size(), ID($sshr)) #undef DEF_METHOD +#define DEF_METHOD(_func, _y_size, _type) \ + RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \ + RTLIL::Cell *cell = addCell(name, _type); \ + cell->parameters[ID::A_SIGNED] = false; \ + cell->parameters[ID::B_SIGNED] = is_signed; \ + cell->parameters[ID::A_WIDTH] = sig_a.size(); \ + cell->parameters[ID::B_WIDTH] = sig_b.size(); \ + cell->parameters[ID::Y_WIDTH] = sig_y.size(); \ + cell->setPort(ID::A, sig_a); \ + cell->setPort(ID::B, sig_b); \ + cell->setPort(ID::Y, sig_y); \ + cell->set_src_attribute(src); \ + return cell; \ + } \ + RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \ + RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \ + add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \ + return sig_y; \ + } +DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx)) +#undef DEF_METHOD + #define DEF_METHOD(_func, _type, _pmux) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ From 777624ccf582410dbb510849d9bff9b23dae0e82 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 24 Jun 2024 16:08:08 +0200 Subject: [PATCH 31/37] Make yosys-config dependant of Makefile --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 73ea0bcc1..858e15a76 100644 --- a/Makefile +++ b/Makefile @@ -736,7 +736,7 @@ CXXFLAGS_NOVERIFIC = $(CXXFLAGS) LIBS_NOVERIFIC = $(LIBS) endif -$(PROGRAM_PREFIX)yosys-config: misc/yosys-config.in +$(PROGRAM_PREFIX)yosys-config: misc/yosys-config.in $(YOSYS_SRC)/Makefile $(P) $(SED) -e 's#@CXXFLAGS@#$(subst -Ilibs/dlfcn-win32,,$(subst -I. -I"$(YOSYS_SRC)",-I"$(DATDIR)/include",$(strip $(CXXFLAGS_NOVERIFIC))))#;' \ -e 's#@CXX@#$(strip $(CXX))#;' -e 's#@LINKFLAGS@#$(strip $(LINKFLAGS) $(PLUGIN_LINKFLAGS))#;' -e 's#@LIBS@#$(strip $(LIBS_NOVERIFIC) $(PLUGIN_LIBS))#;' \ -e 's#@BINDIR@#$(strip $(BINDIR))#;' -e 's#@DATDIR@#$(strip $(DATDIR))#;' < $< > $(PROGRAM_PREFIX)yosys-config From 1288166f7ac03456b6beb0acff5d4fc84f63f57c Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 25 Jun 2024 00:17:11 +0000 Subject: [PATCH 32/37] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 18c39920f..f08c6c3bb 100644 --- a/Makefile +++ b/Makefile @@ -143,7 +143,7 @@ LIBS += -lrt endif endif -YOSYS_VER := 0.42+30 +YOSYS_VER := 0.42+36 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 580aaa362d837559de663ef72cab1384f37481c3 Mon Sep 17 00:00:00 2001 From: Catherine Date: Fri, 28 Jun 2024 15:12:36 +0000 Subject: [PATCH 33/37] opt_lut_ins: fix name of global object. NFCI --- passes/opt/opt_lut_ins.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc index 652fce1e2..d482f652b 100644 --- a/passes/opt/opt_lut_ins.cc +++ b/passes/opt/opt_lut_ins.cc @@ -278,7 +278,7 @@ struct OptLutInsPass : public Pass { module->remove(cell); } } -} XilinxDffOptPass; +} OptLutInsPass; PRIVATE_NAMESPACE_END From a739e21a5f3b4fdd888d4c62f1578a1300c43f00 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 29 Jun 2024 00:16:56 +0000 Subject: [PATCH 34/37] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index f08c6c3bb..313de44d5 100644 --- a/Makefile +++ b/Makefile @@ -143,7 +143,7 @@ LIBS += -lrt endif endif -YOSYS_VER := 0.42+36 +YOSYS_VER := 0.42+40 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From c6e5e0b26ba2f7fd2ecadb3084c93ef9d1858fab Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 9 Jul 2024 09:11:59 +0200 Subject: [PATCH 35/37] Release version 0.43 --- CHANGELOG | 11 ++++++++++- Makefile | 6 +++--- docs/source/conf.py | 2 +- 3 files changed, 14 insertions(+), 5 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index d8e13b041..7148e138a 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,8 +2,17 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.42 .. Yosys 0.43-dev +Yosys 0.42 .. Yosys 0.43 -------------------------- + * Various + - C++ compiler with C++17 support is required. + - Support for IO liberty files for verification. + - Limit padding from shiftadd for "peepopt" pass. + + * Verific support + - Support building Yosys with various Verific library + configurations. Can be built now without YosysHQ + specific patch and extension library. Yosys 0.41 .. Yosys 0.42 -------------------------- diff --git a/Makefile b/Makefile index 313de44d5..1dec716e2 100644 --- a/Makefile +++ b/Makefile @@ -20,7 +20,7 @@ ENABLE_VERIFIC := 0 ENABLE_VERIFIC_SYSTEMVERILOG := 1 ENABLE_VERIFIC_VHDL := 1 ENABLE_VERIFIC_HIER_TREE := 1 -ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1 +ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0 ENABLE_VERIFIC_EDIF := 0 ENABLE_VERIFIC_LIBERTY := 0 ENABLE_COVER := 1 @@ -143,7 +143,7 @@ LIBS += -lrt endif endif -YOSYS_VER := 0.42+40 +YOSYS_VER := 0.43 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -159,7 +159,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9b6afcf.. | wc -l`/;" Makefile +# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9b6afcf.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) diff --git a/docs/source/conf.py b/docs/source/conf.py index c9c923e82..1dd53e954 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -5,7 +5,7 @@ import os project = 'YosysHQ Yosys' author = 'YosysHQ GmbH' copyright ='2024 YosysHQ GmbH' -yosys_ver = "0.42" +yosys_ver = "0.43" # select HTML theme html_theme = 'furo' From ead4718e567aed2e552dcfe46294b132aa04c158 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 9 Jul 2024 09:22:37 +0200 Subject: [PATCH 36/37] Enable extensions for CI --- .github/workflows/test-verific.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index 54d9487ac..5b6268a2e 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -39,6 +39,7 @@ jobs: echo "ENABLE_VERIFIC := 1" >> Makefile.conf echo "ENABLE_VERIFIC_EDIF := 1" >> Makefile.conf echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1" >> Makefile.conf echo "ENABLE_CCACHE := 1" >> Makefile.conf make -j${{ env.procs }} From b9181aaad2cbebc11834ec765fd06bf34af2b634 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 9 Jul 2024 09:27:23 +0200 Subject: [PATCH 37/37] Next dev cycle --- CHANGELOG | 3 +++ Makefile | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 7148e138a..160f480e7 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,9 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.43 .. Yosys 0.44-dev +-------------------------- + Yosys 0.42 .. Yosys 0.43 -------------------------- * Various diff --git a/Makefile b/Makefile index 1dec716e2..2f1c9a016 100644 --- a/Makefile +++ b/Makefile @@ -143,7 +143,7 @@ LIBS += -lrt endif endif -YOSYS_VER := 0.43 +YOSYS_VER := 0.43+0 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -159,7 +159,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: -# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9b6afcf.. | wc -l`/;" Makefile + sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline ead4718.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)