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Share common tests

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This commit is contained in:
Miodrag Milanovic 2019-10-18 12:19:59 +02:00
parent ab98f2dccf
commit 5603595e5c
103 changed files with 179 additions and 1317 deletions
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40
tests/arch/ice40/mux.ys
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@ -1,8 +1,40 @@
read_verilog mux.v
read_verilog ../common/mux.v
design -save read
hierarchy -top mux2
proc
flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 19 t:SB_LUT4
cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top mux4
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 2 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top mux8
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 5 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-count 11 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D