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Share common tests

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This commit is contained in:
Miodrag Milanovic 2019-10-18 12:19:59 +02:00
parent ab98f2dccf
commit 5603595e5c
103 changed files with 179 additions and 1317 deletions
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35
tests/arch/ice40/latches.ys
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@ -1,12 +1,33 @@
read_verilog latches.v
read_verilog ../common/latches.v
design -save read
hierarchy -top latchp
proc
flatten
# Can't run any sort of equivalence check because latches are blown to LUTs
#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
#design -load preopt
synth_ice40
cd top
select -assert-count 4 t:SB_LUT4
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top latchn
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top latchsr
proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D