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Share common tests

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This commit is contained in:
Miodrag Milanovic 2019-10-18 12:19:59 +02:00
parent ab98f2dccf
commit 5603595e5c
103 changed files with 179 additions and 1317 deletions
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6
tests/arch/ice40/fsm.ys
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@ -1,10 +1,10 @@
read_verilog fsm.v
hierarchy -top top
read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
cd fsm # Constrain all select calls below inside the top module
select -assert-count 2 t:SB_DFFESR
select -assert-count 2 t:SB_DFFSR