mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-31 23:34:57 +00:00
Code Activity

Share common tests

Browse source
This commit is contained in:
Miodrag Milanovic 2019-10-18 12:19:59 +02:00
parent ab98f2dccf
commit 5603595e5c
103 changed files with 179 additions and 1317 deletions
Download patch file Download diff file Expand all files Collapse all files

19
tests/arch/ice40/dffs.ys
View file

@ -1,10 +1,19 @@
read_verilog dffs.v
hierarchy -top top
read_verilog ../common/dffs.v
design -save read
hierarchy -top dff
proc
flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D
select -assert-none t:SB_DFFE %% t:* %D