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Share common tests

This commit is contained in:
Miodrag Milanovic 2019-10-18 12:19:59 +02:00
parent ab98f2dccf
commit 5603595e5c
103 changed files with 179 additions and 1317 deletions

View file

@ -1,11 +1,39 @@
read_verilog adffs.v
read_verilog ../common/adffs.v
design -save read
hierarchy -top adff
proc
flatten
equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFNS
select -assert-count 2 t:SB_DFFR
select -assert-count 1 t:SB_DFFS
select -assert-count 2 t:SB_LUT4
select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D
cd adff # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFR
select -assert-none t:SB_DFFR %% t:* %D
design -load read
hierarchy -top adffn
proc
equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFR
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_DFFR t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top dffs
proc
equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFSS
select -assert-none t:SB_DFFSS %% t:* %D
design -load read
hierarchy -top ndffnr
proc
equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFNSR
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_DFFNSR t:SB_LUT4 %% t:* %D