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Share common tests

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This commit is contained in:
Miodrag Milanovic 2019-10-18 12:19:59 +02:00
parent ab98f2dccf
commit 5603595e5c
103 changed files with 179 additions and 1317 deletions
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2
tests/arch/efinix/add_sub.ys
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@ -1,4 +1,4 @@
read_verilog add_sub.v
read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check