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Share common tests

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This commit is contained in:
Miodrag Milanovic 2019-10-18 12:19:59 +02:00
parent ab98f2dccf
commit 5603595e5c
103 changed files with 179 additions and 1317 deletions
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18
tests/arch/common/logic.v Normal file
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module top
(
input [0:7] in,
output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
);
assign B1 = in[0] & in[1];
assign B2 = in[0] | in[1];
assign B3 = in[0] ~& in[1];
assign B4 = in[0] ~| in[1];
assign B5 = in[0] ^ in[1];
assign B6 = in[0] ~^ in[1];
assign B7 = ~in[0];
assign B8 = in[0];
assign B9 = in[0:1] && in [2:3];
assign B10 = in[0:1] || in [2:3];
endmodule