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Merge pull request #2817 from YosysHQ/claire/fixemails
Fixing old e-mail addresses and deadnames
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commit
55e8f5061a
325 changed files with 1311 additions and 1308 deletions
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@ -1,11 +1,11 @@
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module top ( out, clk, reset );
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output [7:0] out;
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input clk, reset;
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reg [7:0] out;
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always @(posedge clk, posedge reset)
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if (reset)
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out <= 8'b0;
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else
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out <= out + 1;
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endmodule
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module top ( out, clk, reset );
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output [7:0] out;
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input clk, reset;
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reg [7:0] out;
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always @(posedge clk, posedge reset)
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if (reset)
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out <= 8'b0;
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else
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out <= out + 1;
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endmodule
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@ -1,51 +1,51 @@
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module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );
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input clock,reset,req_0,req_1;
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output gnt_0,gnt_1;
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wire clock,reset,req_0,req_1;
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reg gnt_0,gnt_1;
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parameter SIZE = 3;
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parameter IDLE = 3'b001;
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parameter GNT0 = 3'b010;
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parameter GNT1 = 3'b100;
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parameter GNT2 = 3'b101;
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reg [SIZE-1:0] state;
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reg [SIZE-1:0] next_state;
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always @ (posedge clock)
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begin : FSM
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if (reset == 1'b1) begin
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state <= #1 IDLE;
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gnt_0 <= 0;
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gnt_1 <= 0;
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end
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else
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case(state)
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IDLE : if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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gnt_0 <= 1;
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end else if (req_1 == 1'b1) begin
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gnt_1 <= 1;
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state <= #1 GNT0;
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end else begin
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state <= #1 IDLE;
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end
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GNT0 : if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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end else begin
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gnt_0 <= 0;
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state <= #1 IDLE;
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end
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GNT1 : if (req_1 == 1'b1) begin
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state <= #1 GNT2;
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gnt_1 <= req_0;
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end
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GNT2 : if (req_0 == 1'b1) begin
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state <= #1 GNT1;
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gnt_1 <= req_1;
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end
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default : state <= #1 IDLE;
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endcase
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end
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endmodule
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module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );
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input clock,reset,req_0,req_1;
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output gnt_0,gnt_1;
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wire clock,reset,req_0,req_1;
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reg gnt_0,gnt_1;
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parameter SIZE = 3;
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parameter IDLE = 3'b001;
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parameter GNT0 = 3'b010;
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parameter GNT1 = 3'b100;
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parameter GNT2 = 3'b101;
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reg [SIZE-1:0] state;
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reg [SIZE-1:0] next_state;
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always @ (posedge clock)
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begin : FSM
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if (reset == 1'b1) begin
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state <= #1 IDLE;
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gnt_0 <= 0;
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gnt_1 <= 0;
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end
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else
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case(state)
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IDLE : if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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gnt_0 <= 1;
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end else if (req_1 == 1'b1) begin
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gnt_1 <= 1;
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state <= #1 GNT0;
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end else begin
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state <= #1 IDLE;
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end
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GNT0 : if (req_0 == 1'b1) begin
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state <= #1 GNT0;
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end else begin
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gnt_0 <= 0;
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state <= #1 IDLE;
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end
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GNT1 : if (req_1 == 1'b1) begin
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state <= #1 GNT2;
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gnt_1 <= req_0;
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end
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GNT2 : if (req_0 == 1'b1) begin
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state <= #1 GNT1;
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gnt_1 <= req_1;
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end
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default : state <= #1 IDLE;
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endcase
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end
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endmodule
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@ -1,11 +1,11 @@
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module top(out, clk, in);
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output [7:0] out;
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input signed clk, in;
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reg signed [7:0] out = 0;
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always @(posedge clk)
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begin
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out <= out >> 1;
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out[7] <= in;
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end
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endmodule
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module top(out, clk, in);
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output [7:0] out;
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input signed clk, in;
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reg signed [7:0] out = 0;
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always @(posedge clk)
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begin
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out <= out >> 1;
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out[7] <= in;
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end
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endmodule
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@ -1,6 +1,6 @@
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// test cases found using vloghammer
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// https://github.com/cliffordwolf/VlogHammer
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// https://github.com/YosysHQ/VlogHammer
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module test01(a, y);
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input [7:0] a;
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@ -154,7 +154,7 @@ always @*
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o <= i[4*W+:W];
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endmodule
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module cliffordwolf_nonexclusive_select (
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module clairexen_nonexclusive_select (
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input wire x, y, z,
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input wire a, b, c, d,
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output reg o
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end
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endmodule
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module cliffordwolf_freduce (
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module clairexen_freduce (
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input wire [1:0] s,
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input wire a, b, c, d,
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output reg [3:0] o
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@ -167,7 +167,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -load read
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hierarchy -top cliffordwolf_nonexclusive_select
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hierarchy -top clairexen_nonexclusive_select
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prep
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design -save gold
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muxpack
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@ -182,7 +182,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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#design -load read
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#hierarchy -top cliffordwolf_freduce
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#hierarchy -top clairexen_freduce
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#prep
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#design -save gold
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#proc; opt; freduce; opt
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@ -3,7 +3,7 @@
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set -ex
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rm -rf Makefile refdat rtl scripts spec
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wget -N http://www.clifford.at/yosys/nogit/vloghammer_tb.tar.bz2
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wget -N https://yosyshq.net/yosys/nogit/vloghammer_tb.tar.bz2
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tar --strip=1 -xjf vloghammer_tb.tar.bz2
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make clean
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