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abc9: fix SCC issues (#2694)

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* xilinx: add SCC test for DSP48E1

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled

* abc9 to break SCCs using $__ABC9_SCC_BREAKER module

* Add test

* abc9_ops: remove refs to (* abc9_keep *) on wires

* abc9_ops: do not bypass cells in an SCC

* Add myself to CODEOWNERS for abc9*

* Fix compile

* abc9_ops: run -prep_hier before scc

* Fix tests

* Remove bug reference pending fix

* abc9: fix for -prep_hier -dff

* xaiger: restore PI handling

* abc9_ops: -prep_xaiger sigmap

* abc9_ops: -mark_scc -> -break_scc

* abc9: eliminate hard-coded abc9.box from tests

Also tidy up

* Address review
This commit is contained in:
Eddie Hung 2021-03-29 22:01:57 -07:00 • committed by GitHub
parent 687f381b69
commit 55dc5a4e4f
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9 changed files with 94 additions and 45 deletions
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12
tests/simple_abc9/run-test.sh
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@ -37,14 +37,18 @@ done
cp ../simple/*.v .
cp ../simple/*.sv .
rm specify.v # bug 2675
DOLLAR='?'
exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-n 300 -p '\
exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-f \"verilog -noblackbox -specify\" -n 300 -p '\
read_verilog -icells -lib +/abc9_model.v; \
hierarchy; \
synth -run coarse; \
opt -full; \
techmap; \
abc9 -lut 4 -box ../abc9.box; \
abc9 -lut 4; \
clean; \
check -assert; \
check -assert * abc9_test037 %d; \
select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \
setattr -mod -unset blackbox'"
setattr -mod -unset blackbox -unset whitebox'"
# NOTE: Skip 'check -assert' on abc9_test037 because it intentionally has a combinatorial loop