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xprop tests: Make iverilog invocation more portable

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This commit is contained in:
Jannis Harder 2023-02-13 16:50:27 +01:00
parent 2a68eee5f1
commit 55ad3fe6c7
1 changed files with 3 additions and 3 deletions
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6
tests/xprop/test.py
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@ -357,15 +357,15 @@ for mode in ["", "_xprop"]:
"-DSIMLIB_FF", "-DSIMLIB_FF",
"-DSIMLIB_GLOBAL_CLOCK=top.gclk", "-DSIMLIB_GLOBAL_CLOCK=top.gclk",
f"-DDUMPFILE=\"vsim_{expr}.vcd\"", f"-DDUMPFILE=\"vsim_{expr}.vcd\"",
"-o",
f"vsim_{expr}",
"verilog_sim_tb.v", "verilog_sim_tb.v",
f"vsim_{expr}.v", f"vsim_{expr}.v",
*simlibs, *simlibs,
"-o",
f"vsim_{expr}",
] ]
) )
with open(f"vsim_{expr}.out", "w") as f: with open(f"vsim_{expr}.out", "w") as f:
subprocess.check_call([f"./vsim_{expr}"], stdout=f) subprocess.check_call(["vvp", f"./vsim_{expr}"], stdout=f)
for mode in ["", "_xprop"]: for mode in ["", "_xprop"]:
if f"sim{mode}" not in steps: if f"sim{mode}" not in steps: