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quicklogic: Add basic k6n10f tests

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Martin Povišer 2023-11-27 12:14:48 +01:00
parent e19833f8c7
commit 554d8caef7
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tests/arch/quicklogic/qlf_k6n10f/counter.ys Normal file
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read_verilog ../../common/counter.v
hierarchy -top top
proc
flatten
equiv_opt -assert -multiclock -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 4 t:$lut
select -assert-count 8 t:adder_carry
select -assert-count 8 t:dffsre
select -assert-none t:$lut t:adder_carry t:dffsre %% t:* %D