mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-09 20:50:51 +00:00
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
This commit:
* renames all remaining instances of "DRAM" (which is ambiguous)
to "LUTRAM" (which is not), finishing the work started in
the commit 698ab9be
;
* renames memory rule files to brams.txt/lutrams.txt;
* adds/renames script labels map_bram/map_lutram;
* extracts where necessary script labels map_ffram and map_gates;
* adds where necessary options -nobram/-nolutram.
The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.
Per architecture:
* anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
:map_lutram, :map_ffram, :map_gates
* ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
* efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
:map_gates
* gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
rename -nodram→-nolutram (-nodram still recognized), rename
:bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
This commit is contained in:
parent
22fe931c86
commit
550310e264
18 changed files with 67 additions and 40 deletions
17
techlibs/gowin/lutrams.txt
Normal file
17
techlibs/gowin/lutrams.txt
Normal file
|
@ -0,0 +1,17 @@
|
|||
bram $__GW1NR_RAM16S4
|
||||
init 1
|
||||
abits 4
|
||||
dbits 4
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 0 1
|
||||
enable 0 1
|
||||
transp 0 1
|
||||
clocks 0 1
|
||||
clkpol 0 1
|
||||
endbram
|
||||
|
||||
match $__GW1NR_RAM16S4
|
||||
make_outreg
|
||||
min wports 1
|
||||
endmatch
|
Loading…
Add table
Add a link
Reference in a new issue