mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-11-04 05:19:11 +00:00 
			
		
		
		
	Fix gcc warning of potentially uninitialised
This commit is contained in:
		
							parent
							
								
									8e56cfb6bb
								
							
						
					
					
						commit
						54f3237720
					
				
					 1 changed files with 2 additions and 2 deletions
				
			
		| 
						 | 
					@ -523,7 +523,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 | 
				
			||||||
		for (auto c : mapped_mod->cells())
 | 
							for (auto c : mapped_mod->cells())
 | 
				
			||||||
		{
 | 
							{
 | 
				
			||||||
			if (c->type == "$_NOT_") {
 | 
								if (c->type == "$_NOT_") {
 | 
				
			||||||
				RTLIL::Cell *cell;
 | 
									RTLIL::Cell *cell = nullptr;
 | 
				
			||||||
				RTLIL::SigBit a_bit = c->getPort("\\A").as_bit();
 | 
									RTLIL::SigBit a_bit = c->getPort("\\A").as_bit();
 | 
				
			||||||
				RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
 | 
									RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
 | 
				
			||||||
				if (!a_bit.wire) {
 | 
									if (!a_bit.wire) {
 | 
				
			||||||
| 
						 | 
					@ -577,7 +577,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 | 
				
			||||||
					cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset));
 | 
										cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset));
 | 
				
			||||||
					cell_stats[RTLIL::unescape_id(c->type)]++;
 | 
										cell_stats[RTLIL::unescape_id(c->type)]++;
 | 
				
			||||||
				}
 | 
									}
 | 
				
			||||||
				if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
 | 
									if (cell && markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
 | 
				
			||||||
				continue;
 | 
									continue;
 | 
				
			||||||
			}
 | 
								}
 | 
				
			||||||
			cell_stats[RTLIL::unescape_id(c->type)]++;
 | 
								cell_stats[RTLIL::unescape_id(c->type)]++;
 | 
				
			||||||
| 
						 | 
					
 | 
				
			||||||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue