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opt_lut: Allow more than one -dlogic per cell type.

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Fixes #2061.
This commit is contained in:
Marcelina Kościelnicka 2021-07-29 16:55:15 +02:00
parent 3156226233
commit 54e75129e5
3 changed files with 55 additions and 24 deletions
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24
tests/arch/ice40/bug2061.ys Normal file
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@ -0,0 +1,24 @@
read_verilog <<EOT
module top #(
parameter integer WIDTH = 12
)(
output reg [WIDTH:0] cnt,
input wire clk,
input wire rst
);
wire last_n;
assign last_n = cnt[WIDTH];
always @(posedge clk or posedge rst)
if (rst)
cnt <= 0;
else
cnt <= last_n ? ( cnt + { (WIDTH+1){last_n} } ) : 13'h1aaa;
endmodule
EOT
synth_ice40
splitnets
select -assert-count 12 t:SB_CARRY %co:+[CO] t:SB_LUT4 %ci:+[I3] %i