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Merge c68fd85b9c into f03b44959b

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Martin Povišer 2025-04-02 14:29:44 +00:00 • committed by GitHub
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6
tests/arch/quicklogic/qlf_k6n10f/dsp.ys → tests/arch/quicklogic/qlf_k6n10f/dspv1_full.ys
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@ -21,7 +21,7 @@ EOF
design -save ast
proc
wreduce
#equiv_opt -async2sync -map +/quicklogic/qlf_k6n10f/dsp_sim.v synth_quicklogic -family qlf_k6n10f
#equiv_opt -async2sync -map +/quicklogic/qlf_k6n10f/dspv1_sim.v synth_quicklogic -family qlf_k6n10f
#design -load postopt
synth_quicklogic -family qlf_k6n10f
cd top
@ -114,8 +114,8 @@ always @(posedge clk) begin
end
endmodule
EOF
read_verilog +/quicklogic/qlf_k6n10f/dsp_sim.v
read_verilog +/quicklogic/qlf_k6n10f/dspv1_sim.v
hierarchy -top testbench
proc
async2sync
sim -assert -q -clock clk -n 20
sim -q -clock clk -n 20 -assert

65
tests/arch/quicklogic/qlf_k6n10f/dspv1_simd.ys Normal file
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@ -0,0 +1,65 @@
read_verilog <<EOT
module foo(
input [7:0] A,
input [7:0] B,
input [7:0] C,
input [7:0] D,
output reg [7:0] X,
output reg [7:0] Y);
assign X = A * B;
assign Y = C * D;
endmodule
EOT
synth_quicklogic -run :map_dsp
# this is just taken from map_dsp step
wreduce t:$mul
ql_dsp_macc
techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=20 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=11 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__QL_MUL20X18
chtype -set $mul t:$__soft_mul
techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9
techmap -map +/quicklogic/qlf_k6n10f/dspv1_map.v -D USE_DSP_CFG_PARAMS=0
read_verilog -lib +/quicklogic/qlf_k6n10f/dspv1_sim.v
read_verilog -lib +/quicklogic/qlf_k6n10f/dspv1_sim_extra.v
select -assert-count 2 t:dsp_t1_10x9x32_cfg_ports
select -assert-count 0 t:dsp_t1_20x18x64_cfg_ports_fracturable
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/dspv1_sim.v -map +/quicklogic/qlf_k6n10f/dspv1_sim_extra.v ql_dsp_simd
design -load postopt
select -assert-count 0 t:dsp_t1_10x9x32_cfg_ports
select -assert-count 1 t:dsp_t1_20x18x64_cfg_ports_fracturable
design -reset
read_verilog <<EOT
module foo(
input [7:0] A,
input [7:0] B,
input [7:0] C,
input [7:0] D,
input [7:0] E,
output reg [7:0] X,
output reg [7:0] Y);
assign X = A * B;
assign Y = C * (D + E); // <-- look here
endmodule
EOT
synth_quicklogic -run :map_dsp
wreduce t:$mul
ql_dsp_macc
techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=20 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=11 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__QL_MUL20X18
chtype -set $mul t:$__soft_mul
techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9
techmap -map +/quicklogic/qlf_k6n10f/dspv1_map.v -D USE_DSP_CFG_PARAMS=0
read_verilog -lib +/quicklogic/qlf_k6n10f/dspv1_sim.v
read_verilog -lib +/quicklogic/qlf_k6n10f/dspv1_sim_extra.v
select -assert-count 2 t:dsp_t1_10x9x32_cfg_ports
select -assert-count 0 t:dsp_t1_20x18x64_cfg_ports_fracturable
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/dspv1_sim.v -map +/quicklogic/qlf_k6n10f/dspv1_sim_extra.v ql_dsp_simd
design -load postopt
select -assert-count 0 t:dsp_t1_10x9x32_cfg_ports
select -assert-count 1 t:dsp_t1_20x18x64_cfg_ports_fracturable

174
tests/arch/quicklogic/qlf_k6n10f/dspv2_full_dsp_flow.ys Normal file
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@ -0,0 +1,174 @@
read_verilog <<EOF
module top(input [6:0] a, input [4:0] b, input [4:0] c, input [4:0] d, input [4:0] e, input [4:0] f, output reg [7:0] o);
assign o = (a * b) + (c * d) + (e * f);
endmodule
EOF
design -save gold
synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
check -assert
opt_clean
select -assert-count 1 top/t:QL_DSPV2_MULT
select -assert-count 2 top/t:QL_DSPV2_MULTADD
read_verilog +/quicklogic/qlf_k6n10f/dspv2_sim.v
prep -flatten -top top
design -save gate
design -reset
design -copy-from gate -as gate top
design -copy-from gold -as gold top
async2sync
equiv_make gold gate equiv
opt -fast equiv
equiv_induct equiv
equiv_status -assert equiv
design -reset
read_verilog <<EOF
module top(input signed [3:0] a, input signed [3:0] b, input signed [3:0] c, input signed [3:0] d, output signed [4:0] o);
assign o = (a * b) + (c * d);
endmodule
EOF
design -save gold
synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
check -assert
opt_clean
stat
select -assert-count 1 top/t:QL_DSPV2_MULT
select -assert-count 1 top/t:QL_DSPV2_MULTADD
read_verilog +/quicklogic/qlf_k6n10f/dspv2_sim.v
prep -flatten -top top
design -save gate
design -reset
design -copy-from gate -as gate top
design -copy-from gold -as gold top
async2sync
equiv_make gold gate equiv
opt -fast equiv
equiv_induct equiv
equiv_status -assert equiv
design -reset
read_verilog <<EOF
module top(input signed [16:0] ar, input signed [16:0] ai, input signed [16:0] br, input signed [16:0] bi, output reg signed [33:0] qr, output reg signed [33:0] qi, input clk);
reg signed [33:0] rr, ri, ir, ii;
always @(posedge clk) begin
rr <= ar * br;
ri <= ar * bi;
ir <= ai * br;
ii <= ai * bi;
qr <= rr - ii;
qi <= ir + ri;
end
endmodule
EOF
synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
check -assert
opt_clean
select -assert-count 2 top/t:QL_DSPV2_MULT_REGOUT
select -assert-count 2 top/t:QL_DSPV2_MULTADD_REGOUT
design -reset
read_verilog <<EOF
module top(input signed [16:0] ar, input signed [16:0] ai, input signed [16:0] br, input signed [16:0] bi, output reg signed [33:0] qr, output reg signed [33:0] qi, input clk);
reg signed [16:0] ar_, ai_, br_, bi_;
always @(posedge clk) begin
ar_ <= ar;
ai_ <= ai;
br_ <= br;
bi_ <= bi;
end
reg signed [33:0] rr, ri, ir, ii;
always @(posedge clk) begin
rr <= ar_ * br_;
ri <= ar_ * bi_;
ir <= ai_ * br_;
ii <= ai_ * bi_;
qr <= rr - ii;
qi <= ir + ri;
end
endmodule
EOF
synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
check -assert
opt_clean -purge
select -assert-count 2 top/t:QL_DSPV2_MULT_REGIN_REGOUT
select -assert-count 2 top/t:QL_DSPV2_MULTADD_REGIN_REGOUT
design -reset
read_verilog <<EOF
module top(input [6:0] a, input [4:0] b, input [4:0] c, input [4:0] d, output [7:0] e, output [7:0] f);
assign e = a * b;
assign f = c * d;
endmodule
EOF
design -save gold
synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
check -assert
opt_clean
select -assert-count 1 top/t:QL_DSPV2_MULT
select -assert-count 1 top/c:*
read_verilog +/quicklogic/qlf_k6n10f/dspv2_sim.v
prep -flatten -top top
design -save gate
design -reset
design -copy-from gate -as gate top
design -copy-from gold -as gold top
async2sync
equiv_make gold gate equiv
opt -fast equiv
equiv_induct equiv
equiv_status -assert equiv
design -reset
read_verilog <<EOF
module top(input signed [6:0] a, input signed [4:0] b, input [4:0] c, input [4:0] d, output signed [7:0] e, output [7:0] f);
assign e = a * b;
assign f = c * d;
endmodule
EOF
design -save gold
synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
check -assert
opt_clean
select -assert-count 1 top/t:QL_DSPV2_MULT
select -assert-count 1 top/c:*
read_verilog +/quicklogic/qlf_k6n10f/dspv2_sim.v
prep -flatten -top top
design -save gate
design -reset
design -copy-from gate -as gate top
design -copy-from gold -as gold top
async2sync
equiv_make gold gate equiv
opt -fast equiv
equiv_induct equiv
equiv_status -assert equiv
design -reset
read_verilog <<EOF
module top(input [16:0] a, input [16:0] b, output reg [33:0] o, input clk, input [2:0] j);
reg [16:0] ar;
reg [16:0] br;
always @(posedge clk) begin
ar <= a;
br <= b;
o <= {ar * br, j};
end
endmodule
EOF
synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
check -assert
opt_clean
select -assert-count 1 top/t:QL_DSPV2_MULT_REGIN_REGOUT

45
tests/arch/quicklogic/qlf_k6n10f/dspv2_macc.tcl Normal file
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@ -0,0 +1,45 @@
yosys -import
proc testcase {top} {
log -header "Testcase $top"
log -push
design -load ast
prep -top $top
design -save gold
design -load ast
hierarchy -top $top
synth_quicklogic -family qlf_k6n10f -dspv2 -run :coarse
opt_clean
select -assert-none t:\$mul
stat
dump $top
select -assert-count 1 t:QL_DSPV2_MULTACC
read_verilog +/quicklogic/qlf_k6n10f/dspv2_sim.v
prep -flatten -top $top
design -save gate
design -clear
design -copy-from gate -as gate A:top
design -copy-from gold -as gold A:top
async2sync
equiv_make gold gate equiv
opt -fast equiv
equiv_induct equiv
equiv_status -assert equiv
log -pop
}
read_verilog dspv2_macc.v
design -save ast
testcase "macc_simple"
testcase "macc_simple_clr"
testcase "macc_simple_arst"
testcase "macc_simple_ena"
testcase "macc_simple_arst_clr_ena"
testcase "macc_simple_preacc_clr"
testcase "macc_simple_signed"
testcase "macc_simple_signed_subtract"

145
tests/arch/quicklogic/qlf_k6n10f/dspv2_macc.v Normal file
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@ -0,0 +1,145 @@
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module macc_simple (
input wire clk,
input wire [5:0] A,
input wire [5:0] B,
output reg [8:0] Z
);
always @(posedge clk)
Z <= Z + (A * B);
endmodule
module macc_simple_clr (
input wire clk,
input wire clr,
input wire [5:0] A,
input wire [5:0] B,
output reg [6:0] Z
);
always @(posedge clk)
if (clr) Z <= (A * B);
else Z <= Z + (A * B);
endmodule
module macc_simple_arst (
input wire clk,
input wire rst,
input wire [5:0] A,
input wire [5:0] B,
output reg [8:0] Z
);
always @(posedge clk or posedge rst)
if (rst) Z <= 0;
else Z <= Z + (A * B);
endmodule
module macc_simple_ena (
input wire clk,
input wire ena,
input wire [5:0] A,
input wire [5:0] B,
output reg [8:0] Z
);
always @(posedge clk)
if (ena) Z <= Z + (A * B);
endmodule
module macc_simple_arst_clr_ena (
input wire clk,
input wire rst,
input wire clr,
input wire ena,
input wire [5:0] A,
input wire [5:0] B,
output reg [7:0] Z
);
always @(posedge clk or posedge rst)
if (rst) Z <= 0;
else if (ena) begin
if (clr) Z <= (A * B);
else Z <= Z + (A * B);
end
endmodule
module macc_simple_preacc (
input wire clk,
input wire [4:0] A,
input wire [4:0] B,
output wire [7:0] Z
);
reg [7:0] acc;
assign Z = acc + (A * B);
always @(posedge clk)
acc <= Z;
endmodule
module macc_simple_preacc_clr (
input wire clk,
input wire clr,
input wire [5:0] A,
input wire [5:0] B,
output reg [7:0] Z
);
reg [7:0] acc;
assign Z = (clr) ? (A * B) : (acc + (A * B));
always @(posedge clk)
acc <= Z;
endmodule
module macc_simple_signed (
input wire clk,
input wire signed [4:0] A,
input wire signed [4:0] B,
output reg signed [7:0] Z
);
always @(posedge clk)
Z <= Z + (A * B);
endmodule
module macc_simple_signed_subtract (
input wire clk,
input wire signed [4:0] A,
input wire signed [4:0] B,
output reg signed [7:0] Z
);
always @(posedge clk)
Z <= Z - (A * B);
endmodule

59
tests/arch/quicklogic/qlf_k6n10f/dspv2_simd.ys Normal file
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@ -0,0 +1,59 @@
read_verilog <<EOT
module foo(
input [7:0] A,
input [7:0] B,
input [7:0] C,
input [7:0] D,
output reg [7:0] X,
output reg [7:0] Y);
assign X = A * B;
assign Y = C * D;
endmodule
EOT
synth_quicklogic -dspv2 -run :map_dsp
# this is just taken from map_dsp step
wreduce t:$mul
ql_dsp_macc -dspv2
techmap -map +/mul2dsp.v -map +/quicklogic/qlf_k6n10f/dspv2_map.v -D USE_DSP_CFG_PARAMS=0 -D DSP_SIGNEDONLY -D DSP_A_MAXWIDTH=32 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__MUL32X18
chtype -set $mul t:$__soft_mul
techmap -map +/mul2dsp.v -map +/quicklogic/qlf_k6n10f/dspv2_map.v -D USE_DSP_CFG_PARAMS=0 -D DSP_SIGNEDONLY -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__MUL16X9
read_verilog -lib +/quicklogic/qlf_k6n10f/dspv2_sim.v
select -assert-count 2 t:dspv2_16x9x32_cfg_ports
select -assert-count 0 t:dspv2_32x18x64_cfg_ports
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/dspv2_sim.v ql_dsp_simd -dspv2
design -load postopt
select -assert-count 0 t:dspv2_16x9x32_cfg_ports
select -assert-count 1 t:dspv2_32x18x64_cfg_ports
design -reset
read_verilog <<EOT
module foo(
input [7:0] A,
input [7:0] B,
input [7:0] C,
input [7:0] D,
input [7:0] E,
output reg [7:0] X,
output reg [7:0] Y);
assign X = A * B;
assign Y = C * (D + E); // <-- look here
endmodule
EOT
synth_quicklogic -dspv2 -run :map_dsp
wreduce t:$mul
ql_dsp_macc -dspv2
techmap -map +/mul2dsp.v -map +/quicklogic/qlf_k6n10f/dspv2_map.v -D USE_DSP_CFG_PARAMS=0 -D DSP_SIGNEDONLY -D DSP_A_MAXWIDTH=32 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__MUL32X18
chtype -set $mul t:$__soft_mul
techmap -map +/mul2dsp.v -map +/quicklogic/qlf_k6n10f/dspv2_map.v -D USE_DSP_CFG_PARAMS=0 -D DSP_SIGNEDONLY -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__MUL16X9
read_verilog -lib +/quicklogic/qlf_k6n10f/dspv2_sim.v
select -assert-count 2 t:dspv2_16x9x32_cfg_ports
select -assert-count 0 t:dspv2_32x18x64_cfg_ports
equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/dspv2_sim.v ql_dsp_simd -dspv2
design -load postopt
select -assert-count 0 t:dspv2_16x9x32_cfg_ports
select -assert-count 1 t:dspv2_32x18x64_cfg_ports

2
tests/verific/blackbox_ql.ys
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@ -1,4 +1,4 @@
verific -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v
verific -sv -lib +/quicklogic/qlf_k6n10f/dspv1_sim.v
verific -sv <<EOF
module top (