mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-06-26 18:48:51 +00:00
Code Activity

[docs] nit: usign the right acronym to refer to the right thing

Browse source 
Tiny nit, but the description of `RTLIL::Wire` was using MSB and LSB to refer to the least and most significant *bits* of a wire and not Bytes, which should be referred to using LSb and MSb instead
This commit is contained in:
Amelia Dobis 2026-06-19 17:30:28 -04:00 • committed by GitHub
parent 5d7486115a
commit 54d43d85e3
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
1 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
docs/source/yosys_internals/formats/rtlil_rep.rst
View file

@ -158,8 +158,8 @@ An ``RTLIL::Wire`` object has the following properties:
- The wire name
- A list of attributes
- A width (buses are just wires with a width more than 1)
- Bus direction (MSB to LSB or vice versa)
- Lowest valid bit index (LSB or MSB depending on bus direction)
- Bus direction (MSb to LSb or vice versa)
- Lowest valid bit index (LSb or MSb depending on bus direction)
- If the wire is a port: port number and direction (input/output/inout)
As with modules, the attributes can be Verilog attributes imported by the