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https://github.com/YosysHQ/yosys
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Add initial support for Verific without additional YosysHQ patch
This commit is contained in:
Miodrag Milanovic
parent
74a1dd99ac
commit
54bf9ccf06
2 changed files with 83 additions and 4 deletions
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@ -43,7 +43,9 @@ USING_YOSYS_NAMESPACE
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#endif
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#include "veri_file.h"
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#ifdef VERIFIC_HIER_TREE_SUPPORT
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#include "hier_tree.h"
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#endif
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#include "VeriModule.h"
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#include "VeriWrite.h"
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#include "VeriLibrary.h"
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@ -72,12 +74,16 @@ USING_YOSYS_NAMESPACE
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#endif
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#ifndef YOSYSHQ_VERIFIC_API_VERSION
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# error "Only YosysHQ flavored Verific is supported. Please contact office@yosyshq.com for commercial support for Yosys+Verific."
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#endif
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#warning "Only YosysHQ flavored Verific is fully supported. Please contact office@yosyshq.com for commercial support for Yosys+Verific."
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#else
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#if YOSYSHQ_VERIFIC_API_VERSION < 20230901
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# error "Please update your version of YosysHQ flavored Verific."
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#endif
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#endif
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#ifndef DB_PRESERVE_INITIAL_VALUE
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#error "Verific must have DB_PRESERVE_INITIAL_VALUE compile flag set on"
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#endif
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#ifdef __clang__
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#pragma clang diagnostic pop
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@ -115,9 +121,15 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil
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if (log_verific_callback) {
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string full_message = stringf("%s%s\n", message_prefix.c_str(), message.c_str());
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#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS
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log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile),
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linefile ? linefile->GetLeftLine() : 0, linefile ? linefile->GetLeftCol() : 0,
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linefile ? linefile->GetRightLine() : 0, linefile ? linefile->GetRightCol() : 0, full_message.c_str());
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#else
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log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile),
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linefile ? LineFile::GetLineNo(linefile) : 0, 0,
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linefile ? LineFile::GetLineNo(linefile) : 0, 0, full_message.c_str());
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#endif
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} else {
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if (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_WARNING || msg_type == VERIFIC_PROGRAM_ERROR)
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log_warning_noprefix("%s%s\n", message_prefix.c_str(), message.c_str());
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@ -392,6 +404,7 @@ static const RTLIL::Const verific_const(const char* type_name, const char *value
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return extract_verilog_const(value, allow_string, output_signed);
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}
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#ifdef YOSYSHQ_VERIFIC_API_VERSION
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static const std::string verific_unescape(const char *value)
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{
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std::string val = std::string(value);
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@ -399,6 +412,7 @@ static const std::string verific_unescape(const char *value)
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return val.substr(1,val.size()-2);
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return value;
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}
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#endif
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void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj, Netlist *nl)
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{
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@ -408,8 +422,13 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
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MapIter mi;
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Att *attr;
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#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS
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if (obj->Linefile())
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attributes[ID::src] = stringf("%s:%d.%d-%d.%d", LineFile::GetFileName(obj->Linefile()), obj->Linefile()->GetLeftLine(), obj->Linefile()->GetLeftCol(), obj->Linefile()->GetRightLine(), obj->Linefile()->GetRightCol());
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#else
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if (obj->Linefile())
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attributes[ID::src] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile()));
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#endif
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FOREACH_ATTRIBUTE(obj, mi, attr) {
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if (attr->Key()[0] == ' ' || attr->Value() == nullptr)
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@ -1265,6 +1284,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
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return true;
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}
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#ifdef YOSYSHQ_VERIFIC_API_VERSION
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if (inst->Type() == OPER_YOSYSHQ_SET_TAG)
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{
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RTLIL::SigSpec sig_expr = operatorInport(inst, "expr");
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@ -1301,6 +1321,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
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module->connect(operatorOutput(inst),module->FutureFF(new_verific_id(inst), operatorInput(inst)));
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return true;
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}
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#endif
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#undef IN
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#undef IN1
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@ -2067,6 +2088,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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continue;
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}
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#ifdef YOSYSHQ_VERIFIC_API_VERSION
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if (inst->Type() == PRIM_YOSYSHQ_INITSTATE)
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{
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if (verific_verbose)
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@ -2078,6 +2100,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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if (!mode_keep)
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continue;
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}
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#endif
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if (!mode_keep && verific_sva_prims.count(inst->Type())) {
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if (verific_verbose)
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@ -2680,7 +2703,24 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
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VerificExtensions::ElaborateAndRewrite("work", &verific_params);
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verific_error_msg.clear();
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#endif
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#ifdef VERIFIC_HIER_TREE_SUPPORT
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netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params);
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#else
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if (parameters.size())
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log_warning("Please note that parameters are not propagated during import.\n");
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veri_file::ElaborateAll("work");
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MapIter mi ;
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Verific::Cell *c ;
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Library *l = Libset::Global()->GetLibrary("work");
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FOREACH_CELL_OF_LIBRARY(l,mi,c) {
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MapIter ni ;
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Netlist *nl;
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FOREACH_NETLIST_OF_CELL(c, ni, nl) {
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if (nl)
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nl_todo.emplace(nl->CellBaseName(), nl);
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}
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}
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#endif
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}
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else {
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@ -2737,7 +2777,11 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
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}
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#endif
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#ifdef VERIFIC_HIER_TREE_SUPPORT
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netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params);
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#else
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netlists = veri_file::ElaborateMultipleTop(&veri_modules, &verific_params);
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#endif
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}
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}
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@ -2781,7 +2825,9 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
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#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
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VerificExtensions::Reset();
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#endif
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#ifdef VERIFIC_HIER_TREE_SUPPORT
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hier_tree::DeleteHierarchicalTree();
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#endif
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veri_file::Reset();
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#ifdef VERIFIC_VHDL_SUPPORT
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vhdl_file::Reset();
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@ -3852,6 +3898,7 @@ struct VerificPass : public Pass {
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#endif
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if (veri_lib) veri_libs.InsertLast(veri_lib);
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#ifdef VERIFIC_HIER_TREE_SUPPORT
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Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, ¶meters);
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Netlist *nl;
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int i;
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@ -3859,6 +3906,23 @@ struct VerificPass : public Pass {
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FOREACH_ARRAY_ITEM(netlists, i, nl)
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nl_todo.emplace(nl->CellBaseName(), nl);
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delete netlists;
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#else
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if (parameters.Size())
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log_warning("Please note that parameters are not propagated during import.\n");
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veri_file::ElaborateAll(work.c_str());
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MapIter mi ;
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Verific::Cell *c ;
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Library *l = Libset::Global()->GetLibrary(work.c_str());
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FOREACH_CELL_OF_LIBRARY(l,mi,c) {
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MapIter ni ;
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Netlist *nl;
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FOREACH_NETLIST_OF_CELL(c, ni, nl) {
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if (nl)
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nl_todo.emplace(nl->CellBaseName(), nl);
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}
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}
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#endif
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}
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else
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{
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@ -3949,7 +4013,11 @@ struct VerificPass : public Pass {
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}
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log("Running hier_tree::Elaborate().\n");
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#ifdef VERIFIC_HIER_TREE_SUPPORT
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netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, ¶meters);
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#else
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netlists = veri_file::ElaborateMultipleTop(&veri_modules, ¶meters);
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#endif
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}
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Netlist *nl;
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@ -4026,7 +4094,9 @@ struct VerificPass : public Pass {
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#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
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VerificExtensions::Reset();
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#endif
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#ifdef VERIFIC_HIER_TREE_SUPPORT
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hier_tree::DeleteHierarchicalTree();
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#endif
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veri_file::Reset();
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#ifdef VERIFIC_VHDL_SUPPORT
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vhdl_file::Reset();
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