Add tests for implicit wires in generate blocks.

Signed-off-by: Yannick Lamarre <yan.lamarre@gmail.com>

tests/verilog/genblk_wire.sv

@@ -0,0 +1,20 @@
+module gold(a, b);
+	output wire [1:0] a;
+	input wire [1:0] b;
+	genvar i;
+	for (i = 0; i < 2; i++) begin
+		wire x;
+		assign x = b[i];
+		assign a[i] = x;
+	end
+endmodule
+
+module gate(a, b);
+	output wire [1:0] a;
+	input wire [1:0] b;
+	genvar i;
+	for (i = 0; i < 2; i++) begin
+		assign x = b[i];
+		assign a[i] = x;
+	end
+endmodule

tests/verilog/genblk_wire.ys

@@ -0,0 +1,17 @@
+logger -expect warning "Identifier `\\genblk1[[]0[]]\.x' is implicitly declared." 1
+logger -expect warning "Identifier `\\genblk1[[]1[]]\.x' is implicitly declared." 1
+read_verilog -sv genblk_wire.sv
+logger -check-expected
+
+select -assert-count 1 gate/genblk1[0].x
+select -assert-count 1 gate/genblk1[1].x
+select -assert-count 0 gate/genblk1[2].x
+
+select -assert-count 1 gold/genblk1[0].x
+select -assert-count 1 gold/genblk1[1].x
+select -assert-count 0 gold/genblk1[2].x
+
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert