diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 5fd478ff3..84f2f9d73 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1539,7 +1539,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (dynamic_cast(current_module)) { /* nothing to do here */ } else if (flag_autowire) - log_file_warning(*location.begin.filename, location.begin.line, "Identifier `%s' is implicitly declared.\n", str.c_str()); + log_file_warning(*location.begin.filename, location.begin.line, "Identifier `%s' is implicitly declared.\n", str); else input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str); } @@ -2200,7 +2200,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_file_info(*location.begin.filename, location.begin.line, "\n"); } else if (str == "$warning") { if (sz > 0) - log_file_warning(*location.begin.filename, location.begin.line, "%s.\n", children[0]->str.c_str()); + log_file_warning(*location.begin.filename, location.begin.line, "%s.\n", children[0]->str); else log_file_warning(*location.begin.filename, location.begin.line, "\n"); } else if (str == "$error") { diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 9b679d0aa..d4e78b730 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1032,7 +1032,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin // note that $display, $finish, and $stop are used for synthesis-time DRC so they're not in this list if ((type == AST_FCALL || type == AST_TCALL) && (str == "$strobe" || str == "$monitor" || str == "$time" || str == "$dumpfile" || str == "$dumpvars" || str == "$dumpon" || str == "$dumpoff" || str == "$dumpall")) { - log_file_warning(*location.begin.filename, location.begin.line, "Ignoring call to system %s %s.\n", type == AST_FCALL ? "function" : "task", str.c_str()); + log_file_warning(*location.begin.filename, location.begin.line, "Ignoring call to system %s %s.\n", type == AST_FCALL ? "function" : "task", str); delete_children(); str = std::string(); } @@ -1042,7 +1042,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin str == "$write" || str == "$writeb" || str == "$writeh" || str == "$writeo")) { if (!current_always) { - log_file_warning(*location.begin.filename, location.begin.line, "System task `%s' outside initial or always block is unsupported.\n", str.c_str()); + log_file_warning(*location.begin.filename, location.begin.line, "System task `%s' outside initial or always block is unsupported.\n", str); delete_children(); str = std::string(); } else { diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 661b4ef96..573af336b 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -49,7 +49,7 @@ void ConstParser::log_maybe_loc_error(std::string msg) { } void ConstParser::log_maybe_loc_warn(std::string msg) { - log_file_warning(*loc.begin.filename, loc.begin.line, "%s", msg.c_str()); + log_file_warning(*loc.begin.filename, loc.begin.line, "%s", msg); } // divide an arbitrary length decimal number by two and return the rest