From fb83719745e67ae1bfcd6e977438cbd2bcedf248 Mon Sep 17 00:00:00 2001
From: Leo Moser <leomoser99@gmail.com>
Date: Sat, 9 May 2026 10:28:07 +0200
Subject: [PATCH] memlib: fix documentation for `PORT_<name>_CLK_POL`

Signed-off-by: Leo Moser <leomoser99@gmail.com>
---
 passes/memory/memlib.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/memory/memlib.md b/passes/memory/memlib.md
index f3c0dd937..5ad3f7777 100644
--- a/passes/memory/memlib.md
+++ b/passes/memory/memlib.md
@@ -310,7 +310,7 @@ The port clock is always provided on the memory cell as `PORT_<name>_CLK` signal
 (even if it is also shared).  Shared clocks are also provided as `CLK_<shared_name>`
 signals.
 
-For `anyedge` clocks, the cell gets a `PORT_<name>_CLKPOL` parameter that is set
+For `anyedge` clocks, the cell gets a `PORT_<name>_CLK_POL` parameter that is set
 to 1 for `posedge` clocks and 0 for `negedge` clocks.  If the clock is shared,
 the same information will also be provided as `CLK_<shared_name>_POL` parameter.