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Docs: Split gate-level cells into subpages
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Krystine Sherwin
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6 changed files with 431 additions and 382 deletions
231
docs/source/cell/gate_reg_ff.rst
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231
docs/source/cell/gate_reg_ff.rst
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.. role:: verilog(code)
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:language: Verilog
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Flip-flop cells
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---------------
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The cell types `$_DFF_N_` and `$_DFF_P_` represent d-type flip-flops.
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.. table:: Cell types for basic flip-flops
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======================================= =============
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Verilog Cell Type
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======================================= =============
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:verilog:`always @(negedge C) Q <= D` `$_DFF_N_`
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:verilog:`always @(posedge C) Q <= D` `$_DFF_P_`
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======================================= =============
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The cell types ``$_DFFE_[NP][NP]_`` implement d-type flip-flops with enable. The
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values in the table for these cell types relate to the following Verilog code
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template.
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.. code-block:: verilog
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:force:
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always @(CLK_EDGE C)
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if (EN == EN_LVL)
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Q <= D;
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.. table:: Cell types for gate level logic networks (FFs with enable)
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:name: tab:CellLib_gates_dffe
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================== ============= ============
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:math:`ClkEdge` :math:`EnLvl` Cell Type
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================== ============= ============
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:verilog:`negedge` ``0`` `$_DFFE_NN_`
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:verilog:`negedge` ``1`` `$_DFFE_NP_`
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:verilog:`posedge` ``0`` `$_DFFE_PN_`
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:verilog:`posedge` ``1`` `$_DFFE_PP_`
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================== ============= ============
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The cell types ``$_DFF_[NP][NP][01]_`` implement d-type flip-flops with
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asynchronous reset. The values in the table for these cell types relate to the
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following Verilog code template, where ``RST_EDGE`` is ``posedge`` if
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``RST_LVL`` if ``1``, and ``negedge`` otherwise.
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.. code-block:: verilog
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:force:
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always @(CLK_EDGE C, RST_EDGE R)
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if (R == RST_LVL)
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Q <= RST_VAL;
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else
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Q <= D;
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The cell types ``$_SDFF_[NP][NP][01]_`` implement d-type flip-flops with
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synchronous reset. The values in the table for these cell types relate to the
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following Verilog code template:
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.. code-block:: verilog
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:force:
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always @(CLK_EDGE C)
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if (R == RST_LVL)
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Q <= RST_VAL;
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else
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Q <= D;
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.. table:: Cell types for gate level logic networks (FFs with reset)
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:name: tab:CellLib_gates_adff
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================== ============== ============== ===========================
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:math:`ClkEdge` :math:`RstLvl` :math:`RstVal` Cell Type
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================== ============== ============== ===========================
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:verilog:`negedge` ``0`` ``0`` `$_DFF_NN0_`, `$_SDFF_NN0_`
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:verilog:`negedge` ``0`` ``1`` `$_DFF_NN1_`, `$_SDFF_NN1_`
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:verilog:`negedge` ``1`` ``0`` `$_DFF_NP0_`, `$_SDFF_NP0_`
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:verilog:`negedge` ``1`` ``1`` `$_DFF_NP1_`, `$_SDFF_NP1_`
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:verilog:`posedge` ``0`` ``0`` `$_DFF_PN0_`, `$_SDFF_PN0_`
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:verilog:`posedge` ``0`` ``1`` `$_DFF_PN1_`, `$_SDFF_PN1_`
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:verilog:`posedge` ``1`` ``0`` `$_DFF_PP0_`, `$_SDFF_PP0_`
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:verilog:`posedge` ``1`` ``1`` `$_DFF_PP1_`, `$_SDFF_PP1_`
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================== ============== ============== ===========================
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The cell types ``$_DFFE_[NP][NP][01][NP]_`` implement d-type flip-flops with
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asynchronous reset and enable. The values in the table for these cell types
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relate to the following Verilog code template, where ``RST_EDGE`` is ``posedge``
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if ``RST_LVL`` if ``1``, and ``negedge`` otherwise.
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.. code-block:: verilog
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:force:
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always @(CLK_EDGE C, RST_EDGE R)
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if (R == RST_LVL)
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Q <= RST_VAL;
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else if (EN == EN_LVL)
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Q <= D;
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The cell types ``$_SDFFE_[NP][NP][01][NP]_`` implement d-type flip-flops with
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synchronous reset and enable, with reset having priority over enable. The values
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in the table for these cell types relate to the following Verilog code template:
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.. code-block:: verilog
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:force:
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always @(CLK_EDGE C)
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if (R == RST_LVL)
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Q <= RST_VAL;
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else if (EN == EN_LVL)
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Q <= D;
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The cell types ``$_SDFFCE_[NP][NP][01][NP]_`` implement d-type flip-flops with
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synchronous reset and enable, with enable having priority over reset. The values
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in the table for these cell types relate to the following Verilog code template:
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.. code-block:: verilog
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:force:
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always @(CLK_EDGE C)
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if (EN == EN_LVL)
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if (R == RST_LVL)
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Q <= RST_VAL;
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else
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Q <= D;
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.. table:: Cell types for gate level logic networks (FFs with reset and enable)
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:name: tab:CellLib_gates_adffe
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================== ============== ============== ============= =================================================
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:math:`ClkEdge` :math:`RstLvl` :math:`RstVal` :math:`EnLvl` Cell Type
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================== ============== ============== ============= =================================================
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:verilog:`negedge` ``0`` ``0`` ``0`` `$_DFFE_NN0N_`, `$_SDFFE_NN0N_`, `$_SDFFCE_NN0N_`
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:verilog:`negedge` ``0`` ``0`` ``1`` `$_DFFE_NN0P_`, `$_SDFFE_NN0P_`, `$_SDFFCE_NN0P_`
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:verilog:`negedge` ``0`` ``1`` ``0`` `$_DFFE_NN1N_`, `$_SDFFE_NN1N_`, `$_SDFFCE_NN1N_`
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:verilog:`negedge` ``0`` ``1`` ``1`` `$_DFFE_NN1P_`, `$_SDFFE_NN1P_`, `$_SDFFCE_NN1P_`
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:verilog:`negedge` ``1`` ``0`` ``0`` `$_DFFE_NP0N_`, `$_SDFFE_NP0N_`, `$_SDFFCE_NP0N_`
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:verilog:`negedge` ``1`` ``0`` ``1`` `$_DFFE_NP0P_`, `$_SDFFE_NP0P_`, `$_SDFFCE_NP0P_`
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:verilog:`negedge` ``1`` ``1`` ``0`` `$_DFFE_NP1N_`, `$_SDFFE_NP1N_`, `$_SDFFCE_NP1N_`
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:verilog:`negedge` ``1`` ``1`` ``1`` `$_DFFE_NP1P_`, `$_SDFFE_NP1P_`, `$_SDFFCE_NP1P_`
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:verilog:`posedge` ``0`` ``0`` ``0`` `$_DFFE_PN0N_`, `$_SDFFE_PN0N_`, `$_SDFFCE_PN0N_`
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:verilog:`posedge` ``0`` ``0`` ``1`` `$_DFFE_PN0P_`, `$_SDFFE_PN0P_`, `$_SDFFCE_PN0P_`
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:verilog:`posedge` ``0`` ``1`` ``0`` `$_DFFE_PN1N_`, `$_SDFFE_PN1N_`, `$_SDFFCE_PN1N_`
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:verilog:`posedge` ``0`` ``1`` ``1`` `$_DFFE_PN1P_`, `$_SDFFE_PN1P_`, `$_SDFFCE_PN1P_`
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:verilog:`posedge` ``1`` ``0`` ``0`` `$_DFFE_PP0N_`, `$_SDFFE_PP0N_`, `$_SDFFCE_PP0N_`
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:verilog:`posedge` ``1`` ``0`` ``1`` `$_DFFE_PP0P_`, `$_SDFFE_PP0P_`, `$_SDFFCE_PP0P_`
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:verilog:`posedge` ``1`` ``1`` ``0`` `$_DFFE_PP1N_`, `$_SDFFE_PP1N_`, `$_SDFFCE_PP1N_`
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:verilog:`posedge` ``1`` ``1`` ``1`` `$_DFFE_PP1P_`, `$_SDFFE_PP1P_`, `$_SDFFCE_PP1P_`
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================== ============== ============== ============= =================================================
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The cell types ``$_DFFSR_[NP][NP][NP]_`` implement d-type flip-flops with
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asynchronous set and reset. The values in the table for these cell types relate
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to the following Verilog code template, where ``RST_EDGE`` is ``posedge`` if
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``RST_LVL`` if ``1``, ``negedge`` otherwise, and ``SET_EDGE`` is ``posedge`` if
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``SET_LVL`` if ``1``, ``negedge`` otherwise.
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.. code-block:: verilog
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:force:
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always @(CLK_EDGE C, RST_EDGE R, SET_EDGE S)
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if (R == RST_LVL)
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Q <= 0;
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else if (S == SET_LVL)
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Q <= 1;
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else
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Q <= D;
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.. table:: Cell types for gate level logic networks (FFs with set and reset)
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:name: tab:CellLib_gates_dffsr
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================== ============== ============== ==============
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:math:`ClkEdge` :math:`SetLvl` :math:`RstLvl` Cell Type
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================== ============== ============== ==============
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:verilog:`negedge` ``0`` ``0`` `$_DFFSR_NNN_`
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:verilog:`negedge` ``0`` ``1`` `$_DFFSR_NNP_`
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:verilog:`negedge` ``1`` ``0`` `$_DFFSR_NPN_`
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:verilog:`negedge` ``1`` ``1`` `$_DFFSR_NPP_`
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:verilog:`posedge` ``0`` ``0`` `$_DFFSR_PNN_`
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:verilog:`posedge` ``0`` ``1`` `$_DFFSR_PNP_`
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:verilog:`posedge` ``1`` ``0`` `$_DFFSR_PPN_`
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:verilog:`posedge` ``1`` ``1`` `$_DFFSR_PPP_`
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================== ============== ============== ==============
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The cell types ``$_DFFSRE_[NP][NP][NP][NP]_`` implement d-type flip-flops with
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asynchronous set and reset and enable. The values in the table for these cell
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types relate to the following Verilog code template, where ``RST_EDGE`` is
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``posedge`` if ``RST_LVL`` if ``1``, ``negedge`` otherwise, and ``SET_EDGE`` is
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``posedge`` if ``SET_LVL`` if ``1``, ``negedge`` otherwise.
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.. code-block:: verilog
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:force:
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always @(CLK_EDGE C, RST_EDGE R, SET_EDGE S)
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if (R == RST_LVL)
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Q <= 0;
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else if (S == SET_LVL)
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Q <= 1;
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else if (E == EN_LVL)
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Q <= D;
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.. table:: Cell types for gate level logic networks (FFs with set and reset and enable)
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:name: tab:CellLib_gates_dffsre
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================== ============== ============== ============= ================
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:math:`ClkEdge` :math:`SetLvl` :math:`RstLvl` :math:`EnLvl` Cell Type
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================== ============== ============== ============= ================
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:verilog:`negedge` ``0`` ``0`` ``0`` `$_DFFSRE_NNNN_`
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:verilog:`negedge` ``0`` ``0`` ``1`` `$_DFFSRE_NNNP_`
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:verilog:`negedge` ``0`` ``1`` ``0`` `$_DFFSRE_NNPN_`
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:verilog:`negedge` ``0`` ``1`` ``1`` `$_DFFSRE_NNPP_`
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:verilog:`negedge` ``1`` ``0`` ``0`` `$_DFFSRE_NPNN_`
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:verilog:`negedge` ``1`` ``0`` ``1`` `$_DFFSRE_NPNP_`
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:verilog:`negedge` ``1`` ``1`` ``0`` `$_DFFSRE_NPPN_`
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:verilog:`negedge` ``1`` ``1`` ``1`` `$_DFFSRE_NPPP_`
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:verilog:`posedge` ``0`` ``0`` ``0`` `$_DFFSRE_PNNN_`
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:verilog:`posedge` ``0`` ``0`` ``1`` `$_DFFSRE_PNNP_`
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:verilog:`posedge` ``0`` ``1`` ``0`` `$_DFFSRE_PNPN_`
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:verilog:`posedge` ``0`` ``1`` ``1`` `$_DFFSRE_PNPP_`
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:verilog:`posedge` ``1`` ``0`` ``0`` `$_DFFSRE_PPNN_`
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:verilog:`posedge` ``1`` ``0`` ``1`` `$_DFFSRE_PPNP_`
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:verilog:`posedge` ``1`` ``1`` ``0`` `$_DFFSRE_PPPN_`
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:verilog:`posedge` ``1`` ``1`` ``1`` `$_DFFSRE_PPPP_`
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================== ============== ============== ============= ================
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.. todo:: flip-flops with async load, ``$_ALDFFE?_[NP]{2,3}_``
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.. autocellgroup:: reg_ff
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:members:
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:source:
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:linenos:
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