Merge pull request #5143 from YosysHQ/krys/typedef_struct_global

SystemVerilog: Fix typedef struct in global space

frontends/ast/simplify.cc

@@ -1433,6 +1433,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
 				current_ast_mod->children.push_back(wnode);
 			}
 			basic_prep = true;
+			is_custom_type = false;
 		}
 		break;
 

frontends/verilog/verilog_parser.y

@@ -1855,7 +1855,7 @@ struct_decl:
 	}
 	;
 
-struct_type: struct_union { astbuf2 = $1; } struct_body { $$ = astbuf2; }
+struct_type: struct_union { astbuf2 = $1; astbuf2->is_custom_type = true; } struct_body { $$ = astbuf2; }
 	;
 
 struct_union:

tests/svtypes/typedef_struct_global.ys

@@ -0,0 +1,13 @@
+read_verilog -sv << EOF
+typedef struct packed {
+	logic y;
+	logic x;
+} Vec_2_B;
+
+module top;
+
+	Vec_2_B two_dee;
+	wire foo = two_dee.x;
+
+endmodule
+EOF