3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 19:05:52 +00:00

Add support for variable length Xilinx SRL > 128

This commit is contained in:
Eddie Hung 2019-03-19 17:44:33 -07:00
parent ae2a625d05
commit 5445cd4d00
2 changed files with 68 additions and 18 deletions

View file

@ -165,12 +165,6 @@ struct ShregmapTechXilinx7 : ShregmapTech
}
log_assert(shiftx);
// Cannot implement variable-length shift registers
// greater than 128 since Q31 cannot be output onto
// fabric
if (GetSize(taps) > 128)
return false;
// Only map if $shiftx exclusively covers the shift register
if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int())
return false;