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changes in verilog frontend for new $mem/$memwr WR_EN interface

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Clifford Wolf 2014-07-16 12:23:47 +02:00
parent 765f172211
commit 543551b80a
2 changed files with 6 additions and 7 deletions
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frontends/ast/genrtlil.cc
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@ -1287,9 +1287,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
cell->connections["\\DATA"] = children[1]->genWidthRTLIL(current_module->memories[str]->width);
cell->connections["\\EN"] = children[2]->genRTLIL();
if (cell->connections["\\EN"].width > 1)
cell->connections["\\EN"] = uniop2rtlil(this, "$reduce_bool", 1, cell->connections["\\EN"], false);
cell->parameters["\\MEMID"] = RTLIL::Const(str);
cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width);