mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-25 04:26:01 +00:00
Code Activity

Clean verilog code from not used define block

Browse source
This commit is contained in:
Miodrag Milanovic 2019-10-04 08:27:49 +02:00
parent d37cd267a5
commit 53bc499a90
2 changed files with 0 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

6
tests/xilinx/shifter.v
View file

@ -9,14 +9,8 @@ in
always @(posedge clk)
begin
`ifndef BUG
out <= out >> 1;
out[7] <= in;
`else
out <= out << 1;
out[7] <= in;
`endif
end
endmodule