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Fix the truth table for $_SR_* cells.

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This brings the documented behavior for these cells in line with
$_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S.
The models were already reflecting that behavior.

Also get rid of sim-synth mismatch in the models while we're at it.
This commit is contained in:
Marcelina Kościelnicka 2020-04-11 16:03:19 +02:00
parent 7ad8b24280
commit 53ba3cf718
3 changed files with 21 additions and 26 deletions
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2
techlibs/common/simlib.v
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@ -1633,7 +1633,7 @@ wire [WIDTH-1:0] pos_clr = CLR_POLARITY ? CLR : ~CLR;
genvar i;
generate
for (i = 0; i < WIDTH; i = i+1) begin:bitslices
always @(posedge pos_set[i], posedge pos_clr[i])
always @*
if (pos_clr[i])
Q[i] <= 0;
else if (pos_set[i])