3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-19 20:33:39 +00:00

Fix the truth table for $_SR_* cells.

This brings the documented behavior for these cells in line with
$_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S.
The models were already reflecting that behavior.

Also get rid of sim-synth mismatch in the models while we're at it.
This commit is contained in:
Marcelina Kościelnicka 2020-04-11 16:03:19 +02:00
parent 7ad8b24280
commit 53ba3cf718
3 changed files with 21 additions and 26 deletions

View file

@ -8,15 +8,14 @@ TEMPLATES = [
//-
//- Truth table: S R | Q
//- -----+---
//- {S:0|1} {R:0|1} | x
//- {S:0|1} {R:1|0} | 1
//- {S:1|0} {R:0|1} | 0
//- {S:1|0} {R:1|0} | y
//- - {R:0|1} | 0
//- {S:0|1} - | 1
//- - - | q
//-
module \$_SR_{S:N|P}{R:N|P}_ (S, R, Q);
input S, R;
output reg Q;
always @({S:neg|pos}edge S, {R:neg|pos}edge R) begin
always @* begin
if (R == {R:0|1})
Q <= 0;
else if (S == {S:0|1})