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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor

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This commit is contained in:
Eddie Hung 2020-01-14 11:46:56 -08:00
commit 53a99ade9c
12 changed files with 88 additions and 52 deletions
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60
backends/edif/edif.cc
View file

@ -300,6 +300,26 @@ struct EdifBackend : public Backend {
*f << stringf(" (library DESIGN\n"); *f << stringf(" (library DESIGN\n");
*f << stringf(" (edifLevel 0)\n"); *f << stringf(" (edifLevel 0)\n");
*f << stringf(" (technology (numberDefinition))\n"); *f << stringf(" (technology (numberDefinition))\n");
auto add_prop = [&](IdString name, Const val) {
if ((val.flags & RTLIL::CONST_FLAG_STRING) != 0)
*f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(name), val.decode_string().c_str());
else if (val.bits.size() <= 32 && RTLIL::SigSpec(val).is_fully_def())
*f << stringf("\n (property %s (integer %u))", EDIF_DEF(name), val.as_int());
else {
std::string hex_string = "";
for (size_t i = 0; i < val.bits.size(); i += 4) {
int digit_value = 0;
if (i+0 < val.bits.size() && val.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
if (i+1 < val.bits.size() && val.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
if (i+2 < val.bits.size() && val.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
if (i+3 < val.bits.size() && val.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
hex_string = std::string(digit_str) + hex_string;
}
*f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val.bits), hex_string.c_str());
}
};
for (auto module : sorted_modules) for (auto module : sorted_modules)
{ {
if (module->get_blackbox_attribute()) if (module->get_blackbox_attribute())
@ -323,14 +343,23 @@ struct EdifBackend : public Backend {
else if (!wire->port_input) else if (!wire->port_input)
dir = "OUTPUT"; dir = "OUTPUT";
if (wire->width == 1) { if (wire->width == 1) {
*f << stringf(" (port %s (direction %s))\n", EDIF_DEF(wire->name), dir); *f << stringf(" (port %s (direction %s)", EDIF_DEF(wire->name), dir);
if (attr_properties)
for (auto &p : wire->attributes)
add_prop(p.first, p.second);
*f << ")\n";
RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire)); RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire));
net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name))); net_join_db[sig].insert(stringf("(portRef %s)", EDIF_REF(wire->name)));
} else { } else {
int b[2]; int b[2];
b[wire->upto ? 0 : 1] = wire->start_offset; b[wire->upto ? 0 : 1] = wire->start_offset;
b[wire->upto ? 1 : 0] = wire->start_offset + GetSize(wire) - 1; b[wire->upto ? 1 : 0] = wire->start_offset + GetSize(wire) - 1;
*f << stringf(" (port (array %s %d) (direction %s))\n", EDIF_DEFR(wire->name, port_rename, b[0], b[1]), wire->width, dir); *f << stringf(" (port (array %s %d) (direction %s)", EDIF_DEFR(wire->name, port_rename, b[0], b[1]), wire->width, dir);
if (attr_properties)
for (auto &p : wire->attributes)
add_prop(p.first, p.second);
*f << ")\n";
for (int i = 0; i < wire->width; i++) { for (int i = 0; i < wire->width; i++) {
RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i)); RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i));
net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), GetSize(wire)-i-1)); net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), GetSize(wire)-i-1));
@ -348,27 +377,6 @@ struct EdifBackend : public Backend {
*f << stringf(" (instance %s\n", EDIF_DEF(cell->name)); *f << stringf(" (instance %s\n", EDIF_DEF(cell->name));
*f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type), *f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : ""); lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
auto add_prop = [&](IdString name, Const val) {
if ((val.flags & RTLIL::CONST_FLAG_STRING) != 0)
*f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(name), val.decode_string().c_str());
else if (val.bits.size() <= 32 && RTLIL::SigSpec(val).is_fully_def())
*f << stringf("\n (property %s (integer %u))", EDIF_DEF(name), val.as_int());
else {
std::string hex_string = "";
for (size_t i = 0; i < val.bits.size(); i += 4) {
int digit_value = 0;
if (i+0 < val.bits.size() && val.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
if (i+1 < val.bits.size() && val.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
if (i+2 < val.bits.size() && val.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
if (i+3 < val.bits.size() && val.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
hex_string = std::string(digit_str) + hex_string;
}
*f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val.bits), hex_string.c_str());
}
};
for (auto &p : cell->parameters) for (auto &p : cell->parameters)
add_prop(p.first, p.second); add_prop(p.first, p.second);
if (attr_properties) if (attr_properties)
@ -432,7 +440,11 @@ struct EdifBackend : public Backend {
if (sig == RTLIL::State::S1) if (sig == RTLIL::State::S1)
*f << stringf(" (portRef %c (instanceRef VCC))\n", gndvccy ? 'Y' : 'P'); *f << stringf(" (portRef %c (instanceRef VCC))\n", gndvccy ? 'Y' : 'P');
} }
*f << stringf(" ))\n"); *f << stringf(" )");
if (attr_properties && sig.wire != NULL)
for (auto &p : sig.wire->attributes)
add_prop(p.first, p.second);
*f << stringf("\n )\n");
} }
*f << stringf(" )\n"); *f << stringf(" )\n");
*f << stringf(" )\n"); *f << stringf(" )\n");

27
frontends/aiger/aigerparse.cc
View file

@ -206,7 +206,7 @@ eval_end:
}; };
AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports) AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports)
: design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports) : design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports), aiger_autoidx(autoidx++)
{ {
module = new RTLIL::Module; module = new RTLIL::Module;
module->name = module_name; module->name = module_name;
@ -255,7 +255,7 @@ end_of_header:
else else
log_abort(); log_abort();
RTLIL::Wire* n0 = module->wire("$0"); RTLIL::Wire* n0 = module->wire(stringf("$aiger%d$0", aiger_autoidx));
if (n0) if (n0)
module->connect(n0, State::S0); module->connect(n0, State::S0);
@ -323,18 +323,18 @@ static uint32_t parse_xaiger_literal(std::istream &f)
return from_big_endian(l); return from_big_endian(l);
} }
static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal) RTLIL::Wire* AigerReader::createWireIfNotExists(RTLIL::Module *module, unsigned literal)
{ {
const unsigned variable = literal >> 1; const unsigned variable = literal >> 1;
const bool invert = literal & 1; const bool invert = literal & 1;
RTLIL::IdString wire_name(stringf("$%d%s", variable, invert ? "b" : "")); RTLIL::IdString wire_name(stringf("$aiger%d$%d%s", aiger_autoidx, variable, invert ? "b" : ""));
RTLIL::Wire *wire = module->wire(wire_name); RTLIL::Wire *wire = module->wire(wire_name);
if (wire) return wire; if (wire) return wire;
log_debug2("Creating %s\n", wire_name.c_str()); log_debug2("Creating %s\n", wire_name.c_str());
wire = module->addWire(wire_name); wire = module->addWire(wire_name);
wire->port_input = wire->port_output = false; wire->port_input = wire->port_output = false;
if (!invert) return wire; if (!invert) return wire;
RTLIL::IdString wire_inv_name(stringf("$%d", variable)); RTLIL::IdString wire_inv_name(stringf("$aiger%d$%d", aiger_autoidx, variable));
RTLIL::Wire *wire_inv = module->wire(wire_inv_name); RTLIL::Wire *wire_inv = module->wire(wire_inv_name);
if (wire_inv) { if (wire_inv) {
if (module->cell(wire_inv_name)) return wire; if (module->cell(wire_inv_name)) return wire;
@ -346,7 +346,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
} }
log_debug2("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str()); log_debug2("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
module->addNotGate(stringf("$%d$not", variable), wire_inv, wire); module->addNotGate(stringf("$not$aiger%d$%d", aiger_autoidx, variable), wire_inv, wire);
return wire; return wire;
} }
@ -383,7 +383,7 @@ void AigerReader::parse_xaiger()
else else
log_abort(); log_abort();
RTLIL::Wire* n0 = module->wire("$0"); RTLIL::Wire* n0 = module->wire(stringf("$aiger%d$0", aiger_autoidx));
if (n0) if (n0)
module->connect(n0, State::S0); module->connect(n0, State::S0);
@ -407,13 +407,14 @@ void AigerReader::parse_xaiger()
uint32_t rootNodeID = parse_xaiger_literal(f); uint32_t rootNodeID = parse_xaiger_literal(f);
uint32_t cutLeavesM = parse_xaiger_literal(f); uint32_t cutLeavesM = parse_xaiger_literal(f);
log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM); log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
RTLIL::Wire *output_sig = module->wire(stringf("$%d", rootNodeID)); RTLIL::Wire *output_sig = module->wire(stringf("$aiger%d$%d", aiger_autoidx, rootNodeID));
log_assert(output_sig);
uint32_t nodeID; uint32_t nodeID;
RTLIL::SigSpec input_sig; RTLIL::SigSpec input_sig;
for (unsigned j = 0; j < cutLeavesM; ++j) { for (unsigned j = 0; j < cutLeavesM; ++j) {
nodeID = parse_xaiger_literal(f); nodeID = parse_xaiger_literal(f);
log_debug2("\t%u\n", nodeID); log_debug2("\t%u\n", nodeID);
RTLIL::Wire *wire = module->wire(stringf("$%d", nodeID)); RTLIL::Wire *wire = module->wire(stringf("$aiger%d$%d", aiger_autoidx, nodeID));
log_assert(wire); log_assert(wire);
input_sig.append(wire); input_sig.append(wire);
} }
@ -430,10 +431,10 @@ void AigerReader::parse_xaiger()
log_assert(o.wire == nullptr); log_assert(o.wire == nullptr);
lut_mask[gray] = o.data; lut_mask[gray] = o.data;
} }
RTLIL::Cell *output_cell = module->cell(stringf("$%d$and", rootNodeID)); RTLIL::Cell *output_cell = module->cell(stringf("$and$aiger%d$%d", aiger_autoidx, rootNodeID));
log_assert(output_cell); log_assert(output_cell);
module->remove(output_cell); module->remove(output_cell);
module->addLut(stringf("$%d$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask)); module->addLut(stringf("$lut$aiger%d$%d", aiger_autoidx, rootNodeID), input_sig, output_sig, std::move(lut_mask));
} }
} }
else if (c == 'r') { else if (c == 'r') {
@ -603,7 +604,7 @@ void AigerReader::parse_aiger_ascii()
RTLIL::Wire *o_wire = createWireIfNotExists(module, l1); RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2); RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire); module->addAndGate("$and" + o_wire->name.str(), i1_wire, i2_wire, o_wire);
} }
std::getline(f, line); // Ignore up to start of next line std::getline(f, line); // Ignore up to start of next line
} }
@ -729,7 +730,7 @@ void AigerReader::parse_aiger_binary()
RTLIL::Wire *o_wire = createWireIfNotExists(module, l1); RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2); RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire); module->addAndGate("$and" + o_wire->name.str(), i1_wire, i2_wire, o_wire);
} }
} }

3
frontends/aiger/aigerparse.h
View file

@ -33,6 +33,7 @@ struct AigerReader
RTLIL::Module *module; RTLIL::Module *module;
std::string map_filename; std::string map_filename;
bool wideports; bool wideports;
const int aiger_autoidx;
unsigned M, I, L, O, A; unsigned M, I, L, O, A;
unsigned B, C, J, F; // Optional in AIGER 1.9 unsigned B, C, J, F; // Optional in AIGER 1.9
@ -51,6 +52,8 @@ struct AigerReader
void parse_aiger_ascii(); void parse_aiger_ascii();
void parse_aiger_binary(); void parse_aiger_binary();
void post_process(); void post_process();
RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal);
}; };
YOSYS_NAMESPACE_END YOSYS_NAMESPACE_END

2
passes/cmds/autoname.cc
View file

@ -56,7 +56,7 @@ int autoname_worker(Module *module)
for (auto &conn : cell->connections()) { for (auto &conn : cell->connections()) {
string suffix = stringf("_%s", log_id(conn.first)); string suffix = stringf("_%s", log_id(conn.first));
for (auto bit : conn.second) for (auto bit : conn.second)
if (bit.wire != nullptr && bit.wire->name[0] == '$') { if (bit.wire != nullptr && bit.wire->name[0] == '$' && !bit.wire->port_id) {
IdString new_name(cell->name.str() + suffix); IdString new_name(cell->name.str() + suffix);
int score = wire_score.at(bit.wire); int score = wire_score.at(bit.wire);
if (cell->output(conn.first)) score = 0; if (cell->output(conn.first)) score = 0;

6
passes/techmap/abc9_ops.cc
View file

@ -488,16 +488,16 @@ void reintegrate(RTLIL::Module *module)
// (TODO: Optimise by not cloning unless will increase depth) // (TODO: Optimise by not cloning unless will increase depth)
RTLIL::IdString driver_name; RTLIL::IdString driver_name;
if (GetSize(a_bit.wire) == 1) if (GetSize(a_bit.wire) == 1)
driver_name = stringf("%s$lut", a_bit.wire->name.c_str()); driver_name = stringf("$lut%s", a_bit.wire->name.c_str());
else else
driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset); driver_name = stringf("$lut%s[%d]", a_bit.wire->name.c_str(), a_bit.offset);
driver_lut = mapped_mod->cell(driver_name); driver_lut = mapped_mod->cell(driver_name);
} }
if (!driver_lut) { if (!driver_lut) {
// If a driver couldn't be found (could be from PI or box CI) // If a driver couldn't be found (could be from PI or box CI)
// then implement using a LUT // then implement using a LUT
RTLIL::Cell *cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())), RTLIL::Cell *cell = module->addLut(remap_name(stringf("$lut%s", mapped_cell->name.c_str())),
RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset), RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset), RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
RTLIL::Const::from_string("01")); RTLIL::Const::from_string("01"));

2
techlibs/xilinx/synth_xilinx.cc
View file

@ -518,7 +518,7 @@ struct SynthXilinxPass : public ScriptPass
techmap_args += " -map +/xilinx/arith_map.v"; techmap_args += " -map +/xilinx/arith_map.v";
if (vpr) if (vpr)
techmap_args += " -D _EXPLICIT_CARRY"; techmap_args += " -D _EXPLICIT_CARRY";
else if (abc9) else
techmap_args += " -D _CLB_CARRY"; techmap_args += " -D _CLB_CARRY";
} }
run("techmap " + techmap_args); run("techmap " + techmap_args);

BIN
tests/arch/ecp5/bug1630.il.gz Normal file
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Binary file not shown.

2
tests/arch/ecp5/bug1630.ys Normal file
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@ -0,0 +1,2 @@
read_ilang bug1630.il.gz
abc9 -lut +/ecp5/abc9_5g.lut

8
tests/arch/xilinx/add_sub.ys
View file

@ -4,8 +4,8 @@ proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
select -assert-count 14 t:LUT2 stat
select -assert-count 6 t:MUXCY select -assert-count 16 t:LUT2
select -assert-count 8 t:XORCY select -assert-count 2 t:CARRY4
select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D select -assert-none t:LUT2 t:CARRY4 %% t:* %D

7
tests/arch/xilinx/counter.ys
View file

@ -5,10 +5,9 @@ flatten
equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG select -assert-count 1 t:BUFG
select -assert-count 8 t:FDCE select -assert-count 8 t:FDCE
select -assert-count 1 t:INV select -assert-count 1 t:INV
select -assert-count 7 t:MUXCY select -assert-count 2 t:CARRY4
select -assert-count 8 t:XORCY select -assert-none t:BUFG t:FDCE t:INV t:CARRY4 %% t:* %D
select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D

2
tests/arch/xilinx/fsm.ys
View file

@ -9,7 +9,7 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module cd fsm # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG select -assert-count 1 t:BUFG
select -assert-count 4 t:FDRE select -assert-count 4 t:FDRE
select -assert-count 1 t:FDSE select -assert-count 1 t:FDSE

19
tests/various/autoname.ys Normal file
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@ -0,0 +1,19 @@
read_ilang <<EOT
autoidx 2
module \top
wire output 3 $y
wire input 1 \a
wire input 2 \b
cell $and \b_$and_B
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a
connect \B \b
connect \Y $y
end
end
EOT
autoname