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Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor

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Eddie Hung 2020-01-14 11:46:56 -08:00
commit 53a99ade9c
12 changed files with 88 additions and 52 deletions
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BIN
tests/arch/ecp5/bug1630.il.gz Normal file
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2
tests/arch/ecp5/bug1630.ys Normal file
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@ -0,0 +1,2 @@
read_ilang bug1630.il.gz
abc9 -lut +/ecp5/abc9_5g.lut

8
tests/arch/xilinx/add_sub.ys
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@ -4,8 +4,8 @@ proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 14 t:LUT2
select -assert-count 6 t:MUXCY
select -assert-count 8 t:XORCY
select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D
stat
select -assert-count 16 t:LUT2
select -assert-count 2 t:CARRY4
select -assert-none t:LUT2 t:CARRY4 %% t:* %D

7
tests/arch/xilinx/counter.ys
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@ -5,10 +5,9 @@ flatten
equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDCE
select -assert-count 1 t:INV
select -assert-count 7 t:MUXCY
select -assert-count 8 t:XORCY
select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D
select -assert-count 2 t:CARRY4
select -assert-none t:BUFG t:FDCE t:INV t:CARRY4 %% t:* %D

2
tests/arch/xilinx/fsm.ys
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@ -9,7 +9,7 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 4 t:FDRE
select -assert-count 1 t:FDSE

19
tests/various/autoname.ys Normal file
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@ -0,0 +1,19 @@
read_ilang <<EOT
autoidx 2
module \top
wire output 3 $y
wire input 1 \a
wire input 2 \b
cell $and \b_$and_B
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \a
connect \B \b
connect \Y $y
end
end
EOT
autoname