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Add test example

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This commit is contained in:
Miodrag Milanovic 2023-02-23 14:58:02 +01:00
parent a30894e5fa
commit 53a4f0fb56
4 changed files with 51 additions and 0 deletions
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28
tests/verific/case.sv Normal file
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module top (
input clk,
input [5:0] currentstate,
output reg [1:0] o
);
always @ (posedge clk)
begin
case (currentstate)
5'd1,5'd2, 5'd3:
begin
o <= 2'b01;
end
5'd4:
begin
o <= 2'b10;
end
5'd5,5'd6,5'd7:
begin
o <= 2'b11;
end
default :
begin
o <= 2'b00;
end
endcase
end
endmodule