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Cleaned up CSA tests.

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This commit is contained in:
nella 2026-03-27 16:14:07 +01:00
parent 39d9be2df9
commit 537d67737d
14 changed files with 636 additions and 806 deletions
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138
tests/csa_tree/csa_tree_sub_chains.ys
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@ -100,3 +100,141 @@ select -assert-count 1 t:$add
select -assert-count 1 t:$not
select -assert-none t:$sub
design -reset
read_verilog <<EOT
module alu_sub_3op(
input [7:0] a, b, c,
output [7:0] y
);
assign y = a - b + c;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt_clean
csa_tree
opt_clean
select -assert-count 2 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$alu
select -assert-none t:$sub
design -reset
read_verilog <<EOT
module alu_sub_mixed(
input [7:0] a, b, c, d,
output [7:0] y
);
assign y = a + b - c + d;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt_clean
csa_tree
opt_clean
select -assert-count 3 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$alu
select -assert-none t:$sub
design -reset
read_verilog <<EOT
module alu_sub_all(
input [7:0] a, b, c, d,
output [7:0] y
);
assign y = a - b - c - d;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt_clean
csa_tree
opt_clean
select -assert-count 3 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$alu
select -assert-none t:$sub
design -reset
read_verilog <<EOT
module alu_sub_signed(
input signed [7:0] a, b, c, d,
output signed [9:0] y
);
assign y = a + b - c - d;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt_clean
csa_tree
opt_clean
select -assert-count 3 t:$fa
select -assert-count 1 t:$add
select -assert-none t:$alu
select -assert-none t:$sub
design -reset
read_verilog <<EOT
module macc_sub_mixed(
input [7:0] a, b, c, d,
output [7:0] y
);
assign y = a + b - c + d;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
csa_tree
opt_clean
select -assert-none t:$macc t:$macc_v2 %u
select -assert-min 1 t:$fa
select -assert-count 1 t:$add
design -reset
read_verilog <<EOT
module macc_const(
input [7:0] a, b, c,
output [7:0] y
);
assign y = a + b + c + 8'd42;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
csa_tree
opt_clean
select -assert-none t:$macc t:$macc_v2 %u
select -assert-min 1 t:$fa
select -assert-count 1 t:$add
design -reset
read_verilog <<EOT
module macc_two(
input [7:0] a, b, c, d, e, f, g, h,
output [7:0] y1, y2
);
assign y1 = a + b + c + d;
assign y2 = e + f + g + h;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
csa_tree
opt_clean
select -assert-none t:$macc t:$macc_v2 %u
select -assert-count 4 t:$fa
select -assert-count 2 t:$add
design -reset