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Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

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meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
This commit is contained in:
Udi Finkelstein 2018-10-25 02:37:56 +03:00
parent 11c8a9eb96
commit 536ae16c3a
14 changed files with 78 additions and 14 deletions
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tests/errors/syntax_err09.v Normal file
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@ -0,0 +1,3 @@
module a(input wire x = 1'b0);
endmodule