mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-10 05:00:52 +00:00
Code Activity

Added $global_clock verilog syntax support for creating $ff cells

Browse source
This commit is contained in:
Clifford Wolf 2016-10-14 12:33:56 +02:00
parent ffbb4e992e
commit 53655d173b
8 changed files with 64 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

8
techlibs/common/simlib.v
View file

@ -1382,18 +1382,22 @@ endmodule
`endif
// --------------------------------------------------------
`ifdef SIMLIB_FF
module \$ff (D, Q);
parameter WIDTH = 0;
input [WIDTH-1:0] D;
output [WIDTH-1:0] Q;
output reg [WIDTH-1:0] Q;
assign D = Q;
always @($global_clk) begin
Q <= D;
end
endmodule
`endif
// --------------------------------------------------------
module \$dff (CLK, D, Q);