mirror of
https://github.com/YosysHQ/yosys
synced 2026-04-29 07:13:43 +00:00
kernel: add SwitchRule signal_src
This commit is contained in:
parent
85a17b0366
commit
53585db9f7
2 changed files with 3 additions and 1 deletions
|
|
@ -627,6 +627,7 @@ struct AST_INTERNAL::ProcessGenerator
|
||||||
RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
|
RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
|
||||||
set_src_attr(sw, ast);
|
set_src_attr(sw, ast);
|
||||||
sw->signal = ast->children[0]->genWidthRTLIL(width_hint, sign_hint, &subst_rvalue_map.stdmap());
|
sw->signal = ast->children[0]->genWidthRTLIL(width_hint, sign_hint, &subst_rvalue_map.stdmap());
|
||||||
|
sw->signal_src = ast->children[0]->loc_string();
|
||||||
current_case->switches.push_back(sw);
|
current_case->switches.push_back(sw);
|
||||||
|
|
||||||
for (auto &attr : ast->attributes) {
|
for (auto &attr : ast->attributes) {
|
||||||
|
|
|
||||||
|
|
@ -2553,7 +2553,7 @@ struct RTLIL::CaseRule : public RTLIL::AttrObject
|
||||||
std::vector<RTLIL::SigSpec> compare;
|
std::vector<RTLIL::SigSpec> compare;
|
||||||
std::vector<RTLIL::SyncAction> actions;
|
std::vector<RTLIL::SyncAction> actions;
|
||||||
std::vector<RTLIL::SwitchRule*> switches;
|
std::vector<RTLIL::SwitchRule*> switches;
|
||||||
Const compare_src;
|
RTLIL::Const compare_src;
|
||||||
|
|
||||||
~CaseRule();
|
~CaseRule();
|
||||||
|
|
||||||
|
|
@ -2567,6 +2567,7 @@ struct RTLIL::CaseRule : public RTLIL::AttrObject
|
||||||
struct RTLIL::SwitchRule : public RTLIL::AttrObject
|
struct RTLIL::SwitchRule : public RTLIL::AttrObject
|
||||||
{
|
{
|
||||||
RTLIL::SigSpec signal;
|
RTLIL::SigSpec signal;
|
||||||
|
RTLIL::Const signal_src;
|
||||||
std::vector<RTLIL::CaseRule*> cases;
|
std::vector<RTLIL::CaseRule*> cases;
|
||||||
|
|
||||||
~SwitchRule();
|
~SwitchRule();
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue