diff --git a/kernel/modtools.h b/kernel/modtools.h
index a081c7556..5cd8e3cb2 100644
--- a/kernel/modtools.h
+++ b/kernel/modtools.h
@@ -28,6 +28,22 @@ YOSYS_NAMESPACE_BEGIN
 
 struct ModIndex : public RTLIL::Monitor
 {
+	struct PointerOrderedSigBit : public RTLIL::SigBit {
+		PointerOrderedSigBit(SigBit s) {
+			wire = s.wire;
+			if (wire)
+				offset = s.offset;
+			else
+				data = s.data;
+		}
+		inline bool operator<(const RTLIL::SigBit &other) const {
+			if (wire == other.wire)
+				return wire ? (offset < other.offset) : (data < other.data);
+			if (wire != nullptr && other.wire != nullptr)
+				return wire < other.wire; // look here
+			return (wire != nullptr) < (other.wire != nullptr);
+		}
+	};
 	struct PortInfo {
 		RTLIL::Cell* cell;
 		RTLIL::IdString port;
@@ -77,7 +93,7 @@ struct ModIndex : public RTLIL::Monitor
 
 	SigMap sigmap;
 	RTLIL::Module *module;
-	std::map<RTLIL::SigBit, SigBitInfo> database;
+	std::map<PointerOrderedSigBit, SigBitInfo> database;
 	int auto_reload_counter;
 	bool auto_reload_module;
 
@@ -94,8 +110,11 @@ struct ModIndex : public RTLIL::Monitor
 	{
 		for (int i = 0; i < GetSize(sig); i++) {
 			RTLIL::SigBit bit = sigmap(sig[i]);
-			if (bit.wire)
+			if (bit.wire) {
 				database[bit].ports.erase(PortInfo(cell, port, i));
+				if (!database[bit].is_input && !database[bit].is_output && database[bit].ports.empty())
+					database.erase(bit);
+			}
 		}
 	}
 
@@ -132,11 +151,11 @@ struct ModIndex : public RTLIL::Monitor
 		}
 	}
 
-	void check()
+	bool ok()
 	{
 #ifndef NDEBUG
 		if (auto_reload_module)
-			return;
+			return true;
 
 		for (auto it : database)
 			log_assert(it.first == sigmap(it.first));
@@ -156,11 +175,17 @@ struct ModIndex : public RTLIL::Monitor
 				else if (!(it.second == database_bak.at(it.first)))
 					log("ModuleIndex::check(): Different content for database[%s].\n", log_signal(it.first));
 
-			log_assert(database == database_bak);
+			return false;
 		}
+		return true;
 #endif
 	}
 
+	void check()
+	{
+		log_assert(ok());
+	}
+
 	void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
 	{
 		log_assert(module == cell->module);
diff --git a/tests/unit/kernel/modindexTest.cc b/tests/unit/kernel/modindexTest.cc
new file mode 100644
index 000000000..1921c9a93
--- /dev/null
+++ b/tests/unit/kernel/modindexTest.cc
@@ -0,0 +1,47 @@
+#include <gtest/gtest.h>
+
+#include "kernel/modtools.h"
+#include "kernel/rtlil.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+TEST(ModIndexSwapTest, has)
+{
+    Design* d = new Design;
+    Module* m = d->addModule("$m");
+    Wire* o = m->addWire("$o", 2);
+    o->port_input = true;
+    Wire* i = m->addWire("$i", 2);
+    i->port_input = true;
+    m->fixup_ports();
+    m->addNot("$not", i, o);
+    auto mi = ModIndex(m);
+    mi.reload_module();
+    for (auto [sb, info] : mi.database) {
+        EXPECT_TRUE(mi.database.find(sb) != mi.database.end());
+    }
+    m->swap_names(i, o);
+    for (auto [sb, info] : mi.database) {
+        EXPECT_TRUE(mi.database.find(sb) != mi.database.end());
+    }
+}
+
+TEST(ModIndexDeleteTest, has)
+{
+    if (log_files.empty()) log_files.emplace_back(stdout);
+    Design* d = new Design;
+    Module* m = d->addModule("$m");
+    Wire* w = m->addWire("$w");
+    Wire* o = m->addWire("$o");
+    o->port_output = true;
+    m->fixup_ports();
+    Cell* not_ = m->addNotGate("$not", w, o);
+    auto mi = ModIndex(m);
+    mi.reload_module();
+    mi.dump_db();
+    Wire* a = m->addWire("\\a");
+    not_->setPort(ID::A, a);
+    EXPECT_TRUE(mi.ok());
+}
+
+YOSYS_NAMESPACE_END