mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-13 04:28:18 +00:00
Perform D replacement properly
This commit is contained in:
parent
74eac76699
commit
5344bfe637
|
@ -144,13 +144,22 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
|
||||||
cell->setParam("\\BREG", 1);
|
cell->setParam("\\BREG", 1);
|
||||||
}
|
}
|
||||||
if (st.ffD) {
|
if (st.ffD) {
|
||||||
|
SigSpec D_ = cell->getPort("\\D");
|
||||||
|
SigSpec D = st.ffB->getPort("\\D");
|
||||||
|
SigSpec Q = st.ffB->getPort("\\Q");
|
||||||
|
D_.replace(Q, D);
|
||||||
|
|
||||||
if (st.ffDmux) {
|
if (st.ffDmux) {
|
||||||
|
SigSpec Y = st.ffDmux->getPort("\\Y");
|
||||||
|
SigSpec AB = st.ffDmux->getPort(st.ffDenpol ? "\\B" : "\\A");
|
||||||
SigSpec S = st.ffDmux->getPort("\\S");
|
SigSpec S = st.ffDmux->getPort("\\S");
|
||||||
cell->setPort("\\CED", st.ffBenpol ? S : pm.module->Not(NEW_ID, S));
|
D_.replace(Y, AB);
|
||||||
|
|
||||||
|
cell->setPort("\\CED", st.ffDenpol ? S : pm.module->Not(NEW_ID, S));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
cell->setPort("\\CED", State::S1);
|
cell->setPort("\\CED", State::S1);
|
||||||
cell->setPort("\\D", st.sigD);
|
cell->setPort("\\D", D_);
|
||||||
|
|
||||||
cell->setParam("\\DREG", 1);
|
cell->setParam("\\DREG", 1);
|
||||||
}
|
}
|
||||||
|
|
|
@ -286,11 +286,6 @@ match ffDmux
|
||||||
optional
|
optional
|
||||||
endmatch
|
endmatch
|
||||||
|
|
||||||
code sigD
|
|
||||||
if (ffDmux)
|
|
||||||
sigD.replace(port(ffDmux, \Y), port(ffDmux, ffDenpol ? \B : \A));
|
|
||||||
endcode
|
|
||||||
|
|
||||||
match ffMmux
|
match ffMmux
|
||||||
if param(dsp, \MREG).as_int() == 0
|
if param(dsp, \MREG).as_int() == 0
|
||||||
if nusers(sigM) == 2
|
if nusers(sigM) == 2
|
||||||
|
|
Loading…
Reference in a new issue