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opt_clean: hide it behind -x

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This commit is contained in:
Emil J. Tywoniak 2025-04-10 11:25:13 +02:00
parent 8b6602460c
commit 532f9abc72
1 changed files with 51 additions and 29 deletions
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80
passes/opt/opt_clean.cc
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@ -298,7 +298,7 @@ bool check_public_name(RTLIL::IdString id)
return true; return true;
} }
bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbose) bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool x_mode, bool verbose)
{ {
// `register_signals` and `connected_signals` will help us decide later on // `register_signals` and `connected_signals` will help us decide later on
// on picking representatives out of groups of connected signals // on picking representatives out of groups of connected signals
@ -311,39 +311,48 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
if (ct_reg.cell_known(cell->type)) { if (ct_reg.cell_known(cell->type)) {
bool clk2fflogic = cell->get_bool_attribute(ID(clk2fflogic)); bool clk2fflogic = cell->get_bool_attribute(ID(clk2fflogic));
for (auto &it2 : cell->connections()) for (auto &it2 : cell->connections())
if (clk2fflogic ? it2.first == ID::D : ct_reg.cell_output(cell->type, it2.first)) if (clk2fflogic ? it2.first == ID::D : ct_reg.cell_output(cell->type, it2.first))
register_signals.add(it2.second); register_signals.add(it2.second);
}
for (auto &it2 : cell->connections()) {
connected_signals.add(it2.second);
if (!ct_all.cell_known(cell->type) || ct_all.cell_output(cell->type, it2.first))
maybe_driven_signals.push_back(it2.second);
} }
for (auto &it2 : cell->connections())
connected_signals.add(it2.second);
} }
SigMap assign_map(module); SigMap assign_map(module);
SigPool maybe_driven_signals_bits; if (x_mode) {
for (auto [_, cell] : module->cells_)
for (auto [port, sig] : cell->connections())
if (!ct_all.cell_known(cell->type) || ct_all.cell_output(cell->type, port)) {
log_debug("cell %s drives sig %s\n", log_id(cell), log_signal(sig));
maybe_driven_signals.push_back(sig);
}
for (auto sig : maybe_driven_signals) { SigPool maybe_driven_signals_bits;
for (auto bit : sig) {
maybe_driven_signals_bits.add(assign_map(bit)); for (auto sig : maybe_driven_signals) {
for (auto bit : sig) {
maybe_driven_signals_bits.add(assign_map(bit));
log_debug("bit %s (rep %s) is driven by cell output\n", log_signal(sig), log_signal(assign_map(sig)));
}
} }
} for (auto &it : module->wires_) {
for (auto &it : module->wires_) { RTLIL::SigSpec sig = it.second;
RTLIL::SigSpec sig = it.second; if (it.second->port_id != 0) {
if (it.second->port_id != 0) { maybe_driven_signals_bits.add(assign_map(sig));
maybe_driven_signals_bits.add(assign_map(sig)); log_debug("bit %s (rep %s) is driven by port input\n", log_signal(sig), log_signal(assign_map(sig)));
}
} }
} for (auto &it : module->wires_) {
for (auto &it : module->wires_) { RTLIL::SigSpec sig = it.second;
RTLIL::SigSpec sig = it.second; for (auto bit : sig) {
for (auto bit : sig) { if (!maybe_driven_signals_bits.check(assign_map(bit))) {
if (!maybe_driven_signals_bits.check(assign_map(bit))) { log_debug("add conn %s <-> %s to assign_map\n", log_signal(bit), log_signal(SigBit(State::Sx)));
log("add conn %s <-> %s to assign_map\n", log_signal(bit), log_signal(SigBit(State::Sx))); assign_map.add(bit, SigBit(State::Sx));
assign_map.add(bit, SigBit(State::Sx)); }
} }
} }
} }
// construct a pool of wires which are directly driven by a known celltype, // construct a pool of wires which are directly driven by a known celltype,
// this will influence our choice of representatives // this will influence our choice of representatives
pool<RTLIL::Wire*> direct_wires; pool<RTLIL::Wire*> direct_wires;
@ -619,7 +628,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool verbose)
return did_something; return did_something;
} }
void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool rminit) void rmunused_module(RTLIL::Module *module, bool purge_mode, bool x_mode, bool verbose, bool rminit)
{ {
if (verbose) if (verbose)
log("Finding unused cells or wires in module %s..\n", module->name.c_str()); log("Finding unused cells or wires in module %s..\n", module->name.c_str());
@ -644,10 +653,10 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool
module->design->scratchpad_set_bool("opt.did_something", true); module->design->scratchpad_set_bool("opt.did_something", true);
rmunused_module_cells(module, verbose); rmunused_module_cells(module, verbose);
while (rmunused_module_signals(module, purge_mode, verbose)) { } while (rmunused_module_signals(module, purge_mode, x_mode, verbose)) { }
if (rminit && rmunused_module_init(module, verbose)) if (rminit && rmunused_module_init(module, verbose))
while (rmunused_module_signals(module, purge_mode, verbose)) { } while (rmunused_module_signals(module, purge_mode, x_mode, verbose)) { }
} }
struct OptCleanPass : public Pass { struct OptCleanPass : public Pass {
@ -668,10 +677,14 @@ struct OptCleanPass : public Pass {
log(" -purge\n"); log(" -purge\n");
log(" also remove internal nets if they have a public name\n"); log(" also remove internal nets if they have a public name\n");
log("\n"); log("\n");
log(" -x\n");
log(" handle unconnected bits as x-bit driven\n");
log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
{ {
bool purge_mode = false; bool purge_mode = false;
bool x_mode = false;
log_header(design, "Executing OPT_CLEAN pass (remove unused cells and wires).\n"); log_header(design, "Executing OPT_CLEAN pass (remove unused cells and wires).\n");
log_push(); log_push();
@ -682,6 +695,10 @@ struct OptCleanPass : public Pass {
purge_mode = true; purge_mode = true;
continue; continue;
} }
if (args[argidx] == "-x") {
x_mode = true;
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
@ -700,7 +717,7 @@ struct OptCleanPass : public Pass {
for (auto module : design->selected_whole_modules_warn()) { for (auto module : design->selected_whole_modules_warn()) {
if (module->has_processes_warn()) if (module->has_processes_warn())
continue; continue;
rmunused_module(module, purge_mode, true, true); rmunused_module(module, purge_mode, x_mode, true, true);
} }
if (count_rm_cells > 0 || count_rm_wires > 0) if (count_rm_cells > 0 || count_rm_wires > 0)
@ -737,6 +754,7 @@ struct CleanPass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
{ {
bool purge_mode = false; bool purge_mode = false;
bool x_mode = false;
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) { for (argidx = 1; argidx < args.size(); argidx++) {
@ -744,6 +762,10 @@ struct CleanPass : public Pass {
purge_mode = true; purge_mode = true;
continue; continue;
} }
if (args[argidx] == "-x") {
x_mode = true;
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
@ -762,7 +784,7 @@ struct CleanPass : public Pass {
for (auto module : design->selected_whole_modules()) { for (auto module : design->selected_whole_modules()) {
if (module->has_processes()) if (module->has_processes())
continue; continue;
rmunused_module(module, purge_mode, ys_debug(), true); rmunused_module(module, purge_mode, x_mode, ys_debug(), true);
} }
log_suppressed(); log_suppressed();