From 532188f23900de787ac21ae641be25493b036d9a Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 15 Jul 2024 11:14:47 +0200 Subject: [PATCH] opt_expr: change info message --- passes/opt/opt_expr.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index ba7292daf..ae5a980b1 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -515,7 +515,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (!cells.sort()) { // There might be a combinational loop, or there might be constants on the output of cells. 'check' may find out more. // ...unless this is a coarse-grained cell loop, but not a bit loop, in which case it won't, and all is good. - log("Couldn't topologically sort cells, Yosys performance may be degraded.\nRunning 'check' is recommended.\n"); + log("Couldn't topologically sort cells, optimizing module %s may take a longer time.\n", log_id(module)); } for (auto cell : cells.sorted)